公开(公告)号：US20130238922A1

公开(公告)日：2013-09-12

申请号：US13866205

申请日：2013-04-19

申请人： Curtis Ling ,  Timothy Gallagher ,  Sridhar Ramesh

发明人： Curtis Ling ,  Timothy Gallagher ,  Sridhar Ramesh

IPC分类号： G06F1/32

CPC分类号： H04L7/0033 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3278 ,  H04L12/2801 ,  H04W52/02 ,  Y02D10/157 ,  Y02D50/20 ,  Y02D70/00 ,  Y02D70/168

摘要： A network device may be operable to receive an indication from a cable modem termination system (CMTS) that media access control (MAC) management messages will be transmitted by the CMTS at fixed intervals. Subsequent to receiving the indication, the network device may be operable to power down one or more components of the network device and set a sleep timer to a value equal to an integer multiple of the fixed interval minus a transition period. The network device may power up the one or more components of the network device upon expiration of the sleep timer. The network device may power up the one or more components of the network device upon an amount of traffic in a buffer of the network device reaching a threshold.

摘要翻译： 网络设备可以用于从电缆调制解调器终端系统（CMTS）接收指示，媒体接入控制（MAC）管理消息将由CMTS以固定的间隔发送。 在接收到指示之后，网络设备可以用于对网络设备的一个或多个组件断电并将休眠定时器设置为等于固定间隔减去过渡周期的整数倍的值。 网络设备可以在睡眠定时器到期时为网络设备的一个或多个组件供电。 网络设备可以在网络设备的缓冲器中的业务量达到阈值时对网络设备的一个或多个组件加电。

公开(公告)号：US20130230078A1

公开(公告)日：2013-09-05

申请号：US13783130

申请日：2013-03-01

申请人： Glenn Chang ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher ,  Shanta Murthy Prem Swaroop ,  Curtis Ling

发明人： Glenn Chang ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher ,  Shanta Murthy Prem Swaroop ,  Curtis Ling

IPC分类号： H04H40/90

CPC分类号： H04H40/90 ,  H04N21/6143

摘要： A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

摘要翻译： 直接广播卫星（DBS）接收组件可以包括可以基于由DBS接收组件服务的客户端设备请求的内容在多个配置之间或之间配置的集成电路。 在第一配置中，多个卫星频带可以被集成电路数字化为单个宽带信号。 在第二配置中，卫星频带可以由集成电路数字化为多个单独的窄带信号。 集成电路可以包括多个接收路径，每个接收链包括多个低噪声放大器和多个模数转换器中的相应一个。

公开(公告)号：US20130210347A1

公开(公告)日：2013-08-15

申请号：US13726994

申请日：2012-12-26

申请人： Curtis Ling ,  Timothy Gallagher

发明人： Curtis Ling ,  Timothy Gallagher

IPC分类号： H04B5/00

CPC分类号： H04W4/80 ,  G01S11/06 ,  G06F3/0481 ,  H04B5/00 ,  H04B5/0037 ,  H04B7/18517 ,  H04B17/309 ,  H04B17/318 ,  H04W12/08 ,  H04W52/283 ,  H04W72/0453 ,  H04W76/10 ,  H04W84/18

摘要： A charging device includes an integrated broadband transceiver that is operable to communicate wireless signals at a power level that is below a spurious emissions mask. The wireless signals are communicated over a designated frequency spectrum band via one or more antennas. The wireless signals convey data between the charging device and a communication device via one or more usable channels within the frequency spectrum band utilized by the integrated broadband transceiver. Concurrent with the communicating, charging of the communication device occurs. One or more usable channels within the frequency spectrum band utilized by the integrated broadband transceiver may be detected. The charging and the communication of the wireless signals occurs currently on the same ones or different ones of the one or more antennas. The detected one or more usable channels may be aggregated and utilized for the communication by the integrated broadband transceiver.

摘要翻译： 充电装置包括集成宽带收发器，其可操作以以低于杂散发射掩模的功率电平来传送无线信号。 无线信号经由一个或多个天线在指定的频谱带上传送。 无线信号通过集成宽带收发器使用的频谱带内的一个或多个可用信道在充电装置和通信装置之间传送数据。 与通信同时发生通信装置的充电。 可以检测由集成宽带收发器使用的频谱带内的一个或多个可用信道。 无线信号的充电和通信目前在一个或多个天线的相同或不同的天线上发生。 检测到的一个或多个可用信道可以被聚合并用于由集成宽带收发器进行通信。

公开(公告)号：US20130203343A1

公开(公告)日：2013-08-08

申请号：US13715250

申请日：2012-12-14

申请人： Curtis Ling ,  Timothy Gallagher ,  Glenn Chang

发明人： Curtis Ling ,  Timothy Gallagher ,  Glenn Chang

IPC分类号： H04B7/185

CPC分类号： H04B7/18526 ,  G01S19/42 ,  H04B7/185 ,  H04B7/18515 ,  H04B7/18517 ,  H04B7/18523 ,  H04H20/08 ,  H04H40/90 ,  H04H60/21 ,  H04H60/23 ,  H04J4/00 ,  H04L45/74 ,  H04L61/2007 ,  H04L65/4076 ,  H04N21/4126 ,  H04N21/4343 ,  H04N21/43637 ,  H04N21/4382 ,  H04N21/4405 ,  H04N21/4408 ,  H04N21/441 ,  H04N21/4524 ,  H04N21/4627 ,  H04N21/61 ,  H04N21/6143 ,  H04N21/6193 ,  H04N21/64322 ,  H04W4/023 ,  H04W76/20 ,  H04W84/042 ,  H04W84/10 ,  H04W84/12 ,  H04W88/08 ,  H04W88/16

摘要： A satellite reception assembly that provides satellite television and/or radio service to a customer premises may comprise a wireless interface via which it can communicate with other satellite reception assemblies. Wireless connections between satellite reception assemblies may be utilized for providing satellite content between different satellite customer premises. Wireless connections between satellite reception assemblies may be utilized for offloading traffic from other network connections.

公开(公告)号：US20130141996A1

公开(公告)日：2013-06-06

申请号：US13758211

申请日：2013-02-04

申请人： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

发明人： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC分类号： G11C29/04

CPC分类号： G11C29/00 ,  G06F11/1048 ,  G11C7/1006 ,  G11C29/04 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/4402

摘要： One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.

摘要翻译： 一个或多个电路可以包括对应于特定存储器地址的存储器单元阵列和存储器故障缓解模块。 一个或多个电路可以用于将数据块写入存储器单元阵列。 响应于阵列的一个或多个存储单元故障的检测，写入操作可以包括数据块的第一部分与数据块的第二部分的交换，并将数据块存储到存储器阵列 互换后的细胞。

公开(公告)号：US20130135535A1

公开(公告)日：2013-05-30

申请号：US13687133

申请日：2012-11-28

申请人： Curtis Ling

发明人： Curtis Ling

IPC分类号： H04N5/50

CPC分类号： H04N5/50 ,  H04N21/42222 ,  H04N21/4384

摘要： A device operable to handle channelized media content may generate a prediction that a first channel will be selected for presentation based on a partially-input channel identifier. The device may process the first channel while concurrently processing a second channel, the second channel having been previously selected for presentation. The prediction may be updated upon input of each character of the channel identifier. The prediction may be based on a position of a user's finger on a remote control and/or based on channels being consumed by consumers in a common demographic with the user. The processing of the first channel may comprise partially decoding the first channel and buffering the partially-decoded first channel. Upon said first channel being selected for presentation, the device may read the partially-decoded first channel from memory, further decode the partially-decoded first channel to recover content, and outputting the recovered content.

摘要翻译： 可操作以处理信道化媒体内容的设备可以产生基于部分输入的信道标识符来选择第一信道以进行呈现的预测。 设备可以处理第一信道同时处理第二信道，第二信道先前被选择用于呈现。 可以在输入信道标识符的每个字符时更新预测。 预测可以基于用户的手指在遥控器上的位置和/或基于消费者在与用户的普通人口中消费的频道。 第一信道的处理可以包括对第一信道进行部分解码并缓冲部分解码的第一信道。 在所述第一信道被选择用于呈现时，设备可以从存储器读取部分解码的第一信道，进一步解码部分解码的第一信道以恢复内容，并输出恢复的内容。

公开(公告)号：US20130122847A1

公开(公告)日：2013-05-16

申请号：US13735388

申请日：2013-01-07

申请人： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

发明人： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

IPC分类号： H04B1/10

CPC分类号： H04B1/26 ,  H03D3/007 ,  H03D3/008 ,  H03D3/009 ,  H03D7/14 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0086 ,  H03H11/22 ,  H04B1/10 ,  H04B1/109 ,  H04B1/12 ,  H04B1/30 ,  H04B15/00 ,  H04J1/18 ,  H04L27/34

摘要： Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

公开(公告)号：US08373804B2

公开(公告)日：2013-02-12

申请号：US12184652

申请日：2008-08-01

申请人： Curtis Ling ,  Patrick Tierney ,  Ramakrishna Akella

发明人： Curtis Ling ,  Patrick Tierney ,  Ramakrishna Akella

IPC分类号： H04N5/455 ,  H04N5/50

CPC分类号： H04N5/50 ,  H04N5/4401 ,  H04N5/4446 ,  H04N5/455 ,  H04N21/4263 ,  H04N21/43632 ,  H04N21/4382 ,  H04N21/443

摘要： A tuner includes, in part, one or mixers, one or more filters, one or more variable gain stages, one or more analog to digital converters, and a baseband processor. Each filter is responsive to an associated mixer's output signal. Each variable gain stage is responsive to an associated filter's output. Each analog-to-digital converter is adapted to convert the output signal of an associated variable gain stage to a digital signal. The baseband processor is responsive to the digital signal supplied by the analog-to-digital converter(s). The baseband processor is further configured to supply a signal to be demodulated by a processing unit external to the integrated circuit. The baseband processor performs no or a fraction of the required demodulation functions. The processing unit may be a central processing unit or a graphical processing unit.

摘要翻译： 调谐器部分地包括一个或者混频器，一个或多个滤波器，一个或多个可变增益级，一个或多个模数转换器和基带处理器。 每个滤波器响应于相关混频器的输出信号。 每个可变增益级都响应相关过滤器的输出。 每个模拟 - 数字转换器适于将相关联的可变增益级的输出信号转换为数字信号。 基带处理器响应由模数转换器提供的数字信号。 基带处理器还被配置为提供要由集成电路外部的处理单元解调的信号。 基带处理器执行所需解调功能的任何部分或一部分。 处理单元可以是中央处理单元或图形处理单元。

公开(公告)号：US20120302192A1

公开(公告)日：2012-11-29

申请号：US13568286

申请日：2012-08-07

申请人： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

发明人： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

IPC分类号： H04B1/26

CPC分类号： H04B1/26 ,  H03D3/007 ,  H03D3/008 ,  H03D3/009 ,  H03D7/14 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0086 ,  H03H11/22 ,  H04B1/10 ,  H04B1/109 ,  H04B1/12 ,  H04B1/30 ,  H04B15/00 ,  H04J1/18 ,  H04L27/34

摘要： Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

公开(公告)号：US20120294100A1

公开(公告)日：2012-11-22

申请号：US13285945

申请日：2011-10-31

申请人： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

发明人： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC分类号： G11C29/00

CPC分类号： G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

摘要翻译： 一种用于存储器功率和/或面积减小的方法和装置。 可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。 可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。 灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。 附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。