公开(公告)号：US07913068B2

公开(公告)日：2011-03-22

申请号：US12035109

申请日：2008-02-21

申请人： James J. Bonanno ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Anthony Saporito ,  Chung-Lung Kevin Shum

发明人： James J. Bonanno ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Anthony Saporito ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/42

CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/30174 ,  G06F9/3806

摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.

摘要翻译： 提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。 该系统包括用于保存分支信息的分支目标缓冲器（BTB）。 分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。 该系统还包括执行方法的搜索逻辑。 该方法包括将BTB中的分支地址定位为针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址以从millicode子程序返回。 该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。 搜索逻辑也可以相对于指令解码单元进行异步操作。

公开(公告)号：US07913067B2

公开(公告)日：2011-03-22

申请号：US12034084

申请日：2008-02-20

申请人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, Jr. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

发明人： David S. Hutton ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  John G. Rell, Jr. ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3857 ,  G06F9/3873

摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.

摘要翻译： 提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。 该系统包括在第一执行流水线中执行指令执行的第一执行单元。 该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。 该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行 单元。 该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

公开(公告)号：US07895538B2

公开(公告)日：2011-02-22

申请号：US12033974

申请日：2008-02-20

申请人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

发明人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/68

摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.

摘要翻译： 系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。 该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。 该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。 对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

公开(公告)号：US07870314B2

公开(公告)日：2011-01-11

申请号：US12031897

申请日：2008-02-15

申请人： Brian D. Barrick ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum ,  Aaron Tsai

发明人： Brian D. Barrick ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum ,  Aaron Tsai

IPC分类号： G06F3/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3836

摘要： A method and system for implementing store buffer allocation for variable length store data operations are provided. The method includes receiving a store address request and at least one store data request and stepping through data operations for each of the store data requests and an address range for the store data requests to determine alignment and data steering information used to select a storage buffer destination for the data in the store data requests. The method further includes determining availability of the storage buffer by maintaining a reservation list for each storage buffer, maintaining a count of the number of available entries for each storage buffer, updating the reservation list to reflect a reservation acceptance for designated available entries, and clearing entries upon completion of the processing of store data operations. The method also includes reserving the selected storage buffer when the number of available entries meets or exceeds the number of entries required for the data.

摘要翻译： 提供了一种用于实现可变长度存储数据操作的存储缓冲区分配的方法和系统。 所述方法包括：接收存储地址请求和至少一个存储数据请求，并且逐步地进行存储数据请求中的每一个的数据操作和存储数据请求的地址范围，以确定用于选择存储缓冲目的地的对准和数据指导信息 用于存储数据请求中的数据。 该方法还包括通过维护每个存储缓冲器的预约列表来确定存储缓冲器的可用性，维护每个存储缓冲器的可用条目数的计数，更新预留列表以反映指定的可用条目的预约接受，以及清除 店铺数据处理完成后的条目。 该方法还包括当可用条目的数量满足或超过数据所需的条目数时，保留所选择的存储缓冲器。

公开(公告)号：US07777520B2

公开(公告)日：2010-08-17

申请号：US12031730

申请日：2008-02-15

申请人： Chung-Lung Kevin Shum ,  Scott B. Swaney

发明人： Chung-Lung Kevin Shum ,  Scott B. Swaney

IPC分类号： H03K19/173

CPC分类号： H03K19/0033

摘要： A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latches, where the latches are scan initialized. The system also includes a disable allowance latch (DAL) allocated to the group of latches, where the DAL is a scan-initialized latch. The system further includes a gating function outputting the state value of at least one of the latches in the group to a functional block in the digital design in response to the DAL being in an enabled state and blocking the gating function output in response to the DAL being in a disabled state.

摘要翻译： 提供了一种用于提高影响数字设计中的功能的扫描初始化锁存器的可靠性的系统，方法和装置。 该系统包括一组锁存器，其基于锁存器的状态值影响数字设计中的功能，其中锁存器被扫描初始化。 该系统还包括分配给锁存器组的禁用允许锁存器（DAL），其中DAL是扫描初始化的锁存器。 该系统还包括选通功能，以响应于DAL处于使能状态，将组中的至少一个锁存器的状态值输出到数字设计中的功能块，并响应于DAL阻塞门控功能输出 处于残疾状态。

公开(公告)号：US20090240914A1

公开(公告)日：2009-09-24

申请号：US12051215

申请日：2008-03-19

申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/38

CPC分类号： G06F9/30065 ,  G06F9/3832

摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

公开(公告)号：US20090240889A1

公开(公告)日：2009-09-24

申请号：US12051736

申请日：2008-03-19

申请人： Ka Shan Choy ,  Jennifer A. Navarro ,  Chung-Lung Kevin Shum ,  Aaron Tsai

发明人： Ka Shan Choy ,  Jennifer A. Navarro ,  Chung-Lung Kevin Shum ,  Aaron Tsai

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0815

摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.

摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。

公开(公告)号：US20090216966A1

公开(公告)日：2009-08-27

申请号：US12036695

申请日：2008-02-25

申请人： Chung-Lung Kevin Shum ,  Brian D. Barrick ,  Thomas Koehler ,  Aaron Tsai

发明人： Chung-Lung Kevin Shum ,  Brian D. Barrick ,  Thomas Koehler ,  Aaron Tsai

IPC分类号： G06F12/02

CPC分类号： G06F12/084 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3879

摘要： A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system.

摘要翻译： 一种用于从外部设备存储结果数据的方法，系统和计算机程序产品。 该方法包括从外部设备接收结果数据，在系统接收。 结果数据存储到存储数据缓冲区中。 存储数据缓冲器被系统用于包含通常由系统生成的存储数据。 执行特殊存储指令以将结果数据存储到系统中的存储器中。 特殊商店指令包括商店地址。 所述执行包括基于所提供的指示信息执行所述存储地址的地址计算，以及利用所述系统利用的用于存储由所述系统正常生成的数据的数据路径来更新所述存储数据缓冲器的存储位置。

公开(公告)号：US20090210679A1

公开(公告)日：2009-08-20

申请号：US12031898

申请日：2008-02-15

申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

IPC分类号： G06F9/38

CPC分类号： G06F12/0855 ,  G06F9/3826 ,  G06F9/3834

摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.

摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。

公开(公告)号：US20090210651A1

公开(公告)日：2009-08-20

申请号：US12033351

申请日：2008-02-19

申请人： Aaron Tsai ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum ,  Scott B. Swaney

发明人： Aaron Tsai ,  Bruce C. Giamei ,  Chung-Lung Kevin Shum ,  Scott B. Swaney

IPC分类号： G06F15/00

CPC分类号： G06F9/30032 ,  G06F9/30101 ,  G06F9/3879

摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.

摘要翻译： 流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。 处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。 处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。 该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。 特殊指令的执行在相应的单位启动。 如果执行特殊指令的单元不是LSU，则将数据发送到LSU。 作为执行特殊指令的结果，从LSU接收数据。 数据被提供给请求者。