公开(公告)号：US06731550B2

公开(公告)日：2004-05-04

申请号：US10161501

申请日：2002-05-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C700

CPC classification number: G11C29/808 ,  G11C29/846

Abstract: A redundancy circuit and method are disclosed for replacing at least one defective memory cell in a memory device. The redundancy circuit may include redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of the defective memory cell. The redundancy circuit may further include a plurality of redundant storage circuits for selectively maintaining data values, and redundant control circuitry for selectively and individually accessing a first of the redundant storage circuits based upon the value of the output signal of the redundant decode circuitry.

Abstract translation: 公开了用于替换存储器件中的至少一个有缺陷的存储器单元的冗余电路和方法。 冗余电路可以包括用于选择性地保持存储器件中的有缺陷的存储器单元的地址的冗余解码电路，接收输入地址并产生具有指示输入地址是否对应于缺陷存储器单元的地址的值的输出信号 。 冗余电路还可以包括用于选择性地维护数据值的多个冗余存储电路，以及冗余控制电路，用于基于冗余解码电路的输出信号的值选择性地和单独地访问第一冗余存储电路。

公开(公告)号：US06456519B1

公开(公告)日：2002-09-24

申请号：US09752209

申请日：2000-12-29

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C1122

CPC classification number: G11C11/22

Abstract: A circuit and method are disclosed for asynchronously accessing accessing a ferroelectric memory device. The ferroelectric memory device internally generates timing signals for latching a received address signal and driving the row lines of the device based upon transitions appearing on the received address signal. The circuit receives an address signal and asserts an edge detect signal in response. The address signal is latched following the edge detect a signal being asserted. Address decode circuitry receives the latched address and generates decoded output signals that identify a row of memory cells to be accessed. In this way, a ferroelectric memory device may effectively replace an asynchronous static random access random access memory (SRAM) device.

Abstract translation: 公开了用于异步访问访问铁电存储器件的电路和方法。 铁电存储器件内部产生用于锁存接收到的地址信号的定时信号，并且基于接收的地址信号上出现的转换来驱动器件的行线。 该电路接收地址信号并且响应地断言边缘检测信号。 地址信号在边缘检测到被断言的信号后被锁存。 地址解码电路接收锁存地址并产生识别要访问的一行存储器单元的解码输出信号。 以这种方式，铁电存储器件可以有效地替代异步静态随机存取随机存取存储器（SRAM）器件。

公开(公告)号：US06359819B1

公开(公告)日：2002-03-19

申请号：US09751007

申请日：2000-12-29

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C700

CPC classification number: G11C29/50 ,  G11C11/22

Abstract: A circuit and method for performing a stress test on a ferroelectric memory device. The memory device includes a memory cell array having a plurality of row lines, column lines and plate lines. The memory device further includes test circuitry for receiving at least one test control signal and in response to the at least one test control signal allowing a voltage differential to be applied between the column lines and the plate lines, so that a stress voltage may be applied across each of the memory cells at one time.

Abstract translation: 一种用于在铁电存储器件上执行应力测试的电路和方法。 存储器件包括具有多条行线，列线和板线的存储单元阵列。 存储器件还包括用于接收至少一个测试控制信号的测试电路，并且响应于该至少一个测试控制信号，允许在列线和板线之间施加电压差，使得可施加应力电压 同时跨越每个存储单元。

公开(公告)号：US06347381B1

公开(公告)日：2002-02-12

申请号：US09183491

申请日：1998-10-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F1130

CPC classification number: G11C29/46 ,  G01R31/31701

Abstract: A detection circuit and a test mode circuit incorporating the detection circuit is disclosed. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first drain is connected to a supply voltage. The detection circuit also includes a P-channel transistor having a second source, a second gate, and a second drain, wherein the second source is connected to the first source and the second drain provides an output signal indicative of a supervoltage being applied to the first gate. The test mode circuit also includes a memory access cycle time-out feature override circuit.

Abstract translation: 公开了一种结合检测电路的检测电路和测试模式电路。 检测电路包括具有第一源极，第一栅极和第一漏极的N沟道晶体管，其中第一漏极连接到电源电压。 检测电路还包括具有第二源极，第二栅极和第二漏极的P沟道晶体管，其中第二源极连接到第一源极，而第二漏极提供指示超电压被施加到第一源极的输出信号 第一门 测试模式电路还包括存储器访问周期超时特征覆盖电路。

公开(公告)号：US6144594A

公开(公告)日：2000-11-07

申请号：US587709

申请日：1996-01-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC classification number: G11C7/1045 ,  G11C29/46

Abstract: A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active from the time they are activated, typically when the clock switched from a first to a second logic state, until the clock switches back to the first logic state.

Abstract translation: 一种具有测试模式控制电路的存储器件，该测试模式控制电路响应于Vss引脚上的高电平进入测试模式，或者在存储器件的正常操作期间，Vcc引脚上的低电平向输出引脚供电。 在测试模式下，通常在时钟从第一个逻辑状态切换到第二个逻辑状态直到时钟切换回第一个逻辑状态时，存储器的字线和位线保持激活状态。

公开(公告)号：US6081466A

公开(公告)日：2000-06-27

申请号：US183451

申请日：1998-10-30

Applicant: David C. McClure ,  Tom Youssef

Inventor： David C. McClure ,  Tom Youssef

IPC: G11C29/08 ,  G11C29/34 ,  G11C00/07

CPC classification number: G11C29/08 ,  G11C29/34

Abstract: A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

Abstract translation: 低/零功率存储器件包括取消选择操作模式，其中禁用字线和列激活所需的存储器件的行解码器，列解码器，写解码器，预编码器，后编码器等操作电路，直到等待 存储器件电源电压超过一定阈值。 附带的测试模式电路检测测试模式激活，并覆盖设备的电源故障解除操作模式的应用。 这在上电时立即激活字线和列相关的操作电路，使得器件通过激活的多个字线和列上电，并准备应用压力测试过电压。

公开(公告)号：US6072732A

公开(公告)日：2000-06-06

申请号：US183444

申请日：1998-10-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/22

Abstract: A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected to the same write bit lines through a fuse structure mimic circuit. Responsive to data transitions on the write bit lines, the reset circuit operates to detect the occurrence of a memory operation to the memory cell and generate a reset signal for resetting the memory in preparation for a next write operation. To support substantially simultaneous presentation of write data to both the reset circuit and the memory cell, the fuse structure mimic circuit delays presentation of the write bit line data to the reset circuit. This introduced delay substantially corresponds to a delay in the presentation of the write bit line data to the memory cell resulting from driving the memory cell bit lines through the selectively blowable fuses.

Abstract translation: 诸如静态随机存取存储器（SRAM）的存储器包括至少一个存储器单元。 该存储单元的位线通过列选择通过晶体管和选择性可熔断保险丝选择性地连接到相应的写位线。 复位电路通过熔丝结构模拟电路连接到相同的写位线。 响应于写入位线上的数据转换，复位电路用于检测对存储器单元的存储器操作的发生，并产生用于复位存储器的复位信号以准备下一次写入操作。 为了基本上同时向复位电路和存储单元提供写入数据，熔丝结构模拟电路将写入位线数据的显示延迟到复位电路。 这种引入的延迟基本上对应于通过可选择性地可熔化的熔丝驱动存储单元位线而将写入位线数据呈现给存储器单元的延迟。

公开(公告)号：US6041000A

公开(公告)日：2000-03-21

申请号：US183840

申请日：1998-10-30

Applicant: David C. McClure ,  Tom Youssef

Inventor： David C. McClure ,  Tom Youssef

IPC: G11C7/20 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/781 ,  G11C7/20

Abstract: A circuit and method are provided for generating an initializing signal to a master enable fuse circuit on a redundant line decoder. An initialization pulse may be applied to a master enable circuit having a master enable fuse. The master enable fuse may be coupled to a switched voltage supply powered selectively by battery voltage and external Vcc. A circuit for generating the INITIAL signal determines the transition from a power down state to a powered state. A series of delay elements in a generating circuit generates a predetermined initialization pulse of around 3 ns to 5 ns. Half-latch circuits may be initialized between a first and second voltage threshold. Accordingly, the master enable circuits may be set to the proper initialization states for proper operation and minimum power consumption.

Abstract translation: 提供一种电路和方法，用于在冗余线路解码器上产生一个初始化信号给主机使能熔丝电路。 可以将初始化脉冲施加到具有主使能熔丝的主启动电路。 主启动保险丝可以耦合到由电池电压和外部Vcc选择性供电的开关电压电源。 用于产生INITIAL信号的电路确定从掉电状态到供电状态的转变。 发生电路中的一系列延迟元件产生约3ns至5ns的预定初始化脉冲。 半锁存电路可以在第一和第二电压阈值之间初始化。 因此，可以将主使能电路设置为适当的初始化状态以进行适当的操作和最小功耗。

公开(公告)号：US5825691A

公开(公告)日：1998-10-20

申请号：US858788

申请日：1997-05-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C16/02 ,  G11C17/00 ,  G11C16/04

CPC classification number: G11C7/22 ,  G11C7/14

Abstract: A start write sensing circuit for sensing a start of a write is coupled to a write simulation circuit. The write simulation circuit preferably includes a memory cell replicate to mimic the amount of time required for writing data to the memory cell. The state of the data stored in the memory cell replicate is changed upon the write sensing circuit sensing the start of a write. The memory cell replicate is preferably constructed using the same structure, design, and process as the memory cells of the array so as to accurately simulate the time required for writing data to a memory cell in the array. Upon the write to the memory cell replicate being completed, a write termination signal is generated for terminating the write signal. The write termination signal also is a reset signal for resetting circuits of the array to prepare for the next cycle, whether it be a read or a write.

Abstract translation: 用于感测写入开始的开始写入感测电路耦合到写入模拟电路。 写入模拟电路优选地包括存储器单元复制以模拟将数据写入存储单元所需的时间量。 存储在存储单元复制中的数据的状态在写入感测电路感测写入的开始时被改变。 优选地，使用与阵列的存储器单元相同的结构，设计和处理来构造存储器单元复制，以便精确地模拟将数据写入阵列中的存储器单元所需的时间。 在完成对存储器单元复制的写入时，产生用于终止写入信号的写入终止信号。 写终止信号也是用于复位阵列的电路以准备下一个周期的复位信号，无论是读还是写。

公开(公告)号：US5802004A

公开(公告)日：1998-09-01

申请号：US587728

申请日：1996-01-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/419 ,  G11C5/06 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/06

Abstract: A memory device with a sense amplifier enable line having the same resistance and capacitance as a local wordline. The sense amplifier enable line is made out of the same material, has the same layout, and has the same load placed on as a local wordline, this will make the sense amplifier enable line have the same resistance, capacitance, and load characteristics as a local wordline. The load on the sense amplifier enable line is a combination of the sense amplifier enable line operational circuitry and sense amplifier enable line load circuit.

Abstract translation: 具有与本地字线具有相同电阻和电容的读出放大器使能线的存储器件。 读出放大器使能线由相同的材料制成，具有相同的布局，并且具有与本地字线相同的负载，这将使得读出放大器使能线具有与电阻，电容和负载特性相同的电阻，电容和负载特性 本地字线。 读出放大器使能线上的负载是读出放大器使能线路运行电路和读出放大器使能线路负载电路的组合。