公开(公告)号：US07337420B2

公开(公告)日：2008-02-26

申请号：US11193711

申请日：2005-07-29

申请人： Dureseti Chidambarrao ,  Donald L. Jordan ,  Judith H. McCullen ,  David M. Onsongo ,  Tina Wagner ,  Richard Q. Williams

发明人： Dureseti Chidambarrao ,  Donald L. Jordan ,  Judith H. McCullen ,  David M. Onsongo ,  Tina Wagner ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

摘要翻译： 用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。 布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

公开(公告)号：US20080042174A1

公开(公告)日：2008-02-21

申请号：US11923075

申请日：2007-10-24

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

公开(公告)号：US20080020531A1

公开(公告)日：2008-01-24

申请号：US11458461

申请日：2006-07-19

申请人： Richard Q. Williams ,  Dureseti Chidambarrao ,  John J. Ellis-Monaghan ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik

发明人： Richard Q. Williams ,  Dureseti Chidambarrao ,  John J. Ellis-Monaghan ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/7624 ,  H01L21/823807 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.

摘要翻译： 提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。 在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反 方向。 以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

公开(公告)号：US20070296044A1

公开(公告)日：2007-12-27

申请号：US11850968

申请日：2007-09-06

申请人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

发明人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843

摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

摘要翻译： 本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。 重整的硅化物层具有与未暴露于形成双重氮化硅衬里的硅化物层基本相似的厚度和电阻。 本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分 在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

公开(公告)号：US20070296001A1

公开(公告)日：2007-12-27

申请号：US11425511

申请日：2006-06-21

申请人： Dureseti Chidambarrao ,  David M. Onsongo

发明人： Dureseti Chidambarrao ,  David M. Onsongo

IPC分类号： H01L29/768

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L29/665 ,  H01L29/7843 ,  Y10S438/938

摘要： A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.

摘要翻译： 提供了一种场效应晶体管（“FET”），其包括包括沟道区，第一源极 - 漏极区和第二源极 - 漏极区的有源半导体区。 有源半导体区域的主表面被分成相互排斥的第一部分和第二部分。 第一衬里将第一应力施加到主表面的第一部分，并且第二衬里将第二应力施加到主表面的第二部分。 第一和第二应力分别选自高拉伸应力，高压缩应力和中性应力，第一应力与第二应力不同。 衬垫可以帮助区分在一个操作条件下由FET的第一部分传导的第一工作电流和在不同工作条件下由FET的第二部分传导的第二工作电流。

公开(公告)号：US20070249126A1

公开(公告)日：2007-10-25

申请号：US11308685

申请日：2006-04-21

申请人： Dureseti Chidambarrao ,  Brian Greene ,  John Ellis-Monaghan

发明人： Dureseti Chidambarrao ,  Brian Greene ,  John Ellis-Monaghan

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823814

摘要： A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.

摘要翻译： 提供一种用于制造晶体管结构的结构和方法。 该方法包括以下步骤：（a）提供包括绝缘体上半导体（“SOI”）层的衬底，该衬底通过掩埋电介质层与衬底的主体区域分离。 （b）首先注入SOI层以在SOI层与掩埋介电层的界面处实现预定的掺杂剂浓度。 以及（c）第二次注入所述SOI层以在多晶半导体栅极导体（“多晶硅”）中以及在与所述多晶硅栅极相邻设置的源极和漏极区域中实现预定的掺杂剂浓度，其中所述第一注入的最大深度大于 第二次植入的最大深度。

公开(公告)号：US20070158753A1

公开(公告)日：2007-07-12

申请号：US11306716

申请日：2006-01-09

申请人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

发明人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

公开(公告)号：US07224021B2

公开(公告)日：2007-05-29

申请号：US11162424

申请日：2005-09-09

申请人： Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Huilong Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

摘要翻译： 本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。 具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。 以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。 优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面 区。 与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

公开(公告)号：US20070108531A1

公开(公告)日：2007-05-17

申请号：US11164179

申请日：2005-11-14

申请人： Dureseti Chidambarrao

发明人： Dureseti Chidambarrao

IPC分类号： H01L29/76

CPC分类号： H01L21/76229 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7846

摘要： A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.

摘要翻译： 半导体结构及其制造方法利用具有由隔离沟槽包围的有源区域台面的半导体衬底。 具有第一应力的第一隔离区域位于隔离沟槽中。 具有不同于第一应力的第二应力的第二隔离区也位于隔离沟槽中。 第一隔离区域和第二隔离区域的尺寸和尺寸被设置成对活性区域台面进行旋转剪切应力。

公开(公告)号：US20070096206A1

公开(公告)日：2007-05-03

申请号：US11163908

申请日：2005-11-03

申请人： Dureseti Chidambarrao

发明人： Dureseti Chidambarrao

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

摘要： A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

摘要翻译： finFET及其制造方法包括形成在半导体鳍片的沟道区域上的栅电极。 半导体鳍具有晶体取向和轴向特定的压阻系数。 形成栅电极，该固有应力确定为影响并优选地优化沟道区内的载流子迁移率。 为此，固有应力优选地在栅极电极和半导体鳍片沟道区域内提供与轴向特定的压阻系数相匹配的感应的轴向应力。