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    MOSFET with high angle sidewall gate and contacts for reduced miller capacitance
    1.
    发明授权
    MOSFET with high angle sidewall gate and contacts for reduced miller capacitance 有权
    具有高角度侧壁栅极的MOSFET和用于降低铣刀电容的触点

    公开(公告)号：US07224021B2

    公开(公告)日：2007-05-29

    申请号：US11162424

    申请日：2005-09-09

    申请人： Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Huilong Zhu

    发明人： Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Huilong Zhu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

    摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

    摘要翻译： 本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。 具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。 以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。 优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面 区。 与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

    Sidewall semiconductor transistors
    2.
    发明授权
    Sidewall semiconductor transistors 有权
    侧壁半导体晶体管

    公开(公告)号：US07397081B2

    公开(公告)日：2008-07-08

    申请号：US10905041

    申请日：2004-12-13

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L29/94

    CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

    摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.

    摘要翻译： 一种新颖的晶体管结构及其制造方法。 晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域 通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面 其基本上平行于衬底的顶表面。

    Sidewall semiconductor transistors
    3.
    发明授权
    Sidewall semiconductor transistors 有权
    侧壁半导体晶体管

    公开(公告)号：US07696025B2

    公开(公告)日：2010-04-13

    申请号：US11867840

    申请日：2007-10-05

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

    摘要： A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.

    摘要翻译： 一种新颖的晶体管结构及其制造方法。 首先，提供衬底，半导体区域，栅极介质区域和栅极块。 半导体区域，栅极电介质区域和栅极块在衬底上。 栅极电介质区域夹在半导体区域和栅极块之间。 半导体区域通过栅极电介质区域与栅极块电绝缘。 半导体区域和栅极电介质区域共享基本上垂直于衬底顶表面的界面。 半导体区域和栅极介电区域不共享基本上平行于衬底顶表面的任何界面表面。 接下来，从栅极块形成栅极区域。 然后，在半导体区域中形成第一和第二源极/漏极区域。

    Method for fabricating a semiconductor structure
    4.
    发明授权
    Method for fabricating a semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US07732288B2

    公开(公告)日：2010-06-08

    申请号：US12367764

    申请日：2009-02-09

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Oleg Gluschenkov ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Oleg Gluschenkov ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L29/76 ,  H01L31/062

    CPC分类号： H01L29/0843 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.

    摘要翻译： 一种半导体结构的制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 提供半导体层上的半导体层和栅极堆叠。 半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。 去除第一和第二半导体区域。 除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。

    METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
    5.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE 有权
    制造半导体结构的方法

    公开(公告)号：US20090142894A1

    公开(公告)日：2009-06-04

    申请号：US12367764

    申请日：2009-02-09

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Oleg Gluschenkov ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Oleg Gluschenkov ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0843 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.

    摘要翻译： 一种半导体结构的制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 提供半导体层上的半导体层和栅极堆叠。 半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。 去除第一和第二半导体区域。 除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。

    SIDEWALL SEMICONDUCTOR TRANSISTORS
    6.
    发明申请
    SIDEWALL SEMICONDUCTOR TRANSISTORS 有权
    端子半导体晶体管

    公开(公告)号：US20080286909A1

    公开(公告)日：2008-11-20

    申请号：US11867840

    申请日：2007-10-05

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

    摘要： A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.

    摘要翻译： 一种新颖的晶体管结构及其制造方法。 首先，提供衬底，半导体区域，栅极介质区域和栅极块。 半导体区域，栅极电介质区域和栅极块在衬底上。 栅极电介质区域夹在半导体区域和栅极块之间。 半导体区域通过栅极电介质区域与栅极块电绝缘。 半导体区域和栅极电介质区域共享基本上垂直于衬底顶表面的界面。 半导体区域和栅极介电区域不共享基本上平行于衬底顶表面的任何界面表面。 接下来，从栅极块形成栅极区域。 然后，在半导体区域中形成第一和第二源极/漏极区域。

    SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES
    10.
    发明申请
    SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES 失效
    用于半导体器件的自对准图形蚀刻停止层

    公开(公告)号：US20110092069A1

    公开(公告)日：2011-04-21

    申请号：US12582137

    申请日：2009-10-20

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    IPC分类号： H01L21/3205 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

    摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

    摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。