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    PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE
    73.
    发明申请
    PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE 有权
    相位改变记忆装置，其中放出了所选择的比特币中的泄漏电流，以及用于在相变存储器件的所述被排列的比特中排出漏电流的方法

    公开(公告)号：US20100128517A1

    公开(公告)日：2010-05-27

    申请号：US12560235

    申请日：2009-09-15

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C5/14

    CPC分类号： G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/79

    摘要： A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage.

    摘要翻译： 相变存储器件包括位线偏置单元; 以及位线选择单元，其将所选择的位线连接到所述位线偏置单元，并且在操作状态下将所选择的位线与所述位线偏置单元断开。 位线放电单元连接到位线以排除位线中的泄漏电流。 位线放电单元具有电压调节单元和耦合在电压调节单元和相应位线之间的多个位线放电开关。 控制位线放电开关将取消选择的位线连接到电压调节单元，并将选定的位线与电压调节单元断开。 电压调节单元包括耦合在调节电压总线和参考电位线之间的PMOS晶体管。 调节电压总线连接到位线放电开关，PMOS晶体管的控制端被偏置为恒定电压。

    Circuit for Reading Memory Cells
    74.
    发明申请
    Circuit for Reading Memory Cells 有权
    读取存储单元的电路

    公开(公告)号：US20090285016A1

    公开(公告)日：2009-11-19

    申请号：US12491352

    申请日：2009-06-25

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

    摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

    摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

    Streaming mode programming in phase change memories
    75.
    发明授权
    Streaming mode programming in phase change memories 有权
    流相模式编程在相变存储器中

    公开(公告)号：US07577024B2

    公开(公告)日：2009-08-18

    申请号：US11807125

    申请日：2007-05-25

    申请人： Richard E. Fackenthal ,  Ferdinando Bedeschi ,  Ravi Annavajjhala ,  Giulio Casagrande

    发明人： Richard E. Fackenthal ,  Ferdinando Bedeschi ,  Ravi Annavajjhala ,  Giulio Casagrande

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069

    摘要： A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

    摘要翻译： 可以在相变存储器中的用户命令上实现流式编程模式。 在流式编程模式下，加速编程可以通过升高其用于读取和编程的电压来实现。 重复的编程操作可以在一次斜升之后流式传输，而不会在编程操作之间降低存储器单元上的电压。 这可能会节省时间。 此外，可以在编程操作之间再次读取存储器，而不一定下降。

    Generating reference currents compensated for process variation in non-volatile memories
    76.
    发明申请
    Generating reference currents compensated for process variation in non-volatile memories 有权
    生成参考电流补偿了非易失性存储器中的工艺变化

    公开(公告)号：US20090080267A1

    公开(公告)日：2009-03-26

    申请号：US11904071

    申请日：2007-09-26

    申请人： Ferdinando Bedeschi ,  Claudio Resta ,  Enzo Donze

    发明人： Ferdinando Bedeschi ,  Claudio Resta ,  Enzo Donze

    IPC分类号： G11C5/14 ,  G05F3/02

    CPC分类号： G11C5/147

    摘要： In a current reference generator device, a voltage reference generator stage generates a reference voltage (Vref) and an active element output stage receives the reference voltage (Vref) and outputs a reference current (Iref) as a function of the reference voltage (Vref). A control stage is operatively coupled to the voltage reference generator stage and to the active element output stage and controls a first trimmable parameter (m) associated to the voltage reference generator stage and a second trimmable parameter associated to the active element output stage, so as to compensate for changes in a value of the reference current (Iref) due to manufacturing process deviations.

    摘要翻译： 在电流参考发生器装置中，电压基准发生器级产生参考电压（Vref），并且有源元件输出级接收参考电压（Vref）并输出作为参考电压（Vref）的函数的参考电流（Iref） 。 控制级可操作地耦合到电压参考发生器级和有源元件输出级，并且控制与电压参考发生器级相关联的第一可调整参数（m）和与有源元件输出级相关联的第二可调整参数，以便 以补偿由于制造工艺偏差导致的参考电流（Iref）的值的变化。

    Semiconductor memory device with information loss self-detect capability
    78.
    发明申请
    Semiconductor memory device with information loss self-detect capability 有权
    半导体存储器件具有信息丢失自检能力

    公开(公告)号：US20070253238A1

    公开(公告)日：2007-11-01

    申请号：US11415879

    申请日：2006-05-01

    申请人： Claudio Resta ,  Ferdinando Bedeschi

    发明人： Claudio Resta ,  Ferdinando Bedeschi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/22 ,  G11C11/2275 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0083

    摘要： A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

    摘要翻译： 一种半导体存储器件，包括多个可编程存储器单元，每个可编程存储器单元适于在至少第一状态和第二状态之间变为一个，所述多个存储器单元包括用于存储数据的存储单元，以及用于存取存储器的装置 用于阅读/修改其状态的单元格。 所述多个中的至少一个存储单元被用作检测器存储器单元，并且提供与所述至少一个检测器存储单元可操作地相关联的控制装置，所述控制装置适于建立存储在存储单元中的数据的潜在损耗 所述多个基于所述至少一个检测器存储单元的检测到的第一状态。

    Nonvolatile phase change memory device and biasing method therefor
    79.
    发明授权
    Nonvolatile phase change memory device and biasing method therefor 有权
    非易失相变存储器件及其偏置方法

    公开(公告)号：US07269080B2

    公开(公告)日：2007-09-11

    申请号：US11195359

    申请日：2005-08-02

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C5/14

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

    摘要： A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

    摘要翻译： 一种非易失性相变存储器件，包括由排列成行和列的存储单元形成的存储器阵列，连接到布置在同一行上的存储器单元的第一端子的字线，以及连接到布置在同一列上的存储器单元的第二端子的位线 ; 耦合到所述存储器阵列以偏置所述字线的行解码器; 耦合到存储器阵列以偏置位线的列解码器; 以及耦合到行解码器和列解码器的偏置电路，以向寻址的存储器单元的端子提供第一偏置电压和第二偏置电压，其中第一偏置电压是正偏压，而第二偏压是 负偏压电压。

    Circuit for reading memory cells
    80.
    发明申请
    Circuit for reading memory cells 有权
    读取存储单元的电路

    公开(公告)号：US20060221678A1

    公开(公告)日：2006-10-05

    申请号：US11093879

    申请日：2005-03-30

    申请人： Ferdinando Bedeschi ,  Claudio Resta

    发明人： Ferdinando Bedeschi ,  Claudio Resta

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

    摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

    摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。