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    MOSFET WITH SOURCE SIDE ONLY STRESS
    73.
    发明申请
    MOSFET WITH SOURCE SIDE ONLY STRESS 有权
    MOSFET，源极只有应力

    公开(公告)号：US20120146054A1

    公开(公告)日：2012-06-14

    申请号：US13288170

    申请日：2011-11-03

    申请人： Samuel Zafar Nawaz ,  Shaofeng Yu ,  Jeffrey E. Brighton ,  Song Zhao

    发明人： Samuel Zafar Nawaz ,  Shaofeng Yu ,  Jeffrey E. Brighton ,  Song Zhao

    IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L21/20

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

    摘要： An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

    摘要翻译： 集成电路仅包含源极侧的应力增强区域的晶体管。 在DeMOS晶体管中，仅在源极上形成应力增强区域并且在漏极延伸中不形成应力增强区域增加了漏极延伸区域的电阻，从而能够形成减小面积的DeMOS晶体管。 在MOS晶体管中，通过在源极侧形成应力增强区域，消除来自漏极侧的应力增强区域，降低了晶体管泄漏，提高了CHC可靠性。

    CMOS PROCESS TO IMPROVE SRAM YIELD
    74.
    发明申请
    CMOS PROCESS TO IMPROVE SRAM YIELD 有权
    CMOS工艺改进SRAM输出

    公开(公告)号：US20120104510A1

    公开(公告)日：2012-05-03

    申请号：US13284519

    申请日：2011-10-28

    申请人： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

    发明人： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

    摘要： An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

    摘要翻译： 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

    INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES
    76.
    发明申请
    INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES 有权
    使用直接硅结合（DSB）基板在混合方向技术（热）中改变晶体取向的集成方案

    公开(公告)号：US20110108893A1

    公开(公告)日：2011-05-12

    申请号：US13007098

    申请日：2011-01-14

    申请人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

    发明人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

    IPC分类号： H01L27/092

    CPC分类号： H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

    摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

    摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 诸如非晶化和模板重结晶（ATR）的方法具有制造深亚微米CMOS的缺点。 本发明是形成具有（100）和（110）取向区域的​​集成电路（IC）的方法。 该方法在（100）取向的衬底上形成（110）取向的硅的直接键合的硅（DSB）层。 在NMOS区域中去除DSB层，并且使用基底作为种子层，通过选择性外延生长（SEG）形成（100）取向硅层。 在SEG层上形成NMOS晶体管，而在DSB层上形成PMOS晶体管。 还公开了用本发明方法形成的集成电路。

    LOW COST SYMMETRIC TRANSISTORS
    77.
    发明申请
    LOW COST SYMMETRIC TRANSISTORS 审中-公开
    低成本对称晶体管

    公开(公告)号：US20100327361A1

    公开(公告)日：2010-12-30

    申请号：US12492818

    申请日：2009-06-26

    申请人： KAMEL BENAISSA ,  Greg C. Baldwin ,  Shaofeng Yu

    发明人： KAMEL BENAISSA ,  Greg C. Baldwin ,  Shaofeng Yu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

    摘要： An integrated circuit is disclosed containing two types of MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed.

    摘要翻译： 公开了一种集成电路，其包含相同极性的两种类型的MOS晶体管，它们彼此垂直取向，通过使用角度旋转的子植入物同时进行的光晕离子，LDD离子和/或S / 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。

    IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS
    78.
    发明申请
    IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS 审中-公开
    使用热烘烤工艺减少影响的植入

    公开(公告)号：US20100167472A1

    公开(公告)日：2010-07-01

    申请号：US12646479

    申请日：2009-12-23

    申请人： Yiming Gu ,  Shaofeng Yu ,  James Blatchford

    发明人： Yiming Gu ,  Shaofeng Yu ,  James Blatchford

    IPC分类号： H01L21/335 ,  G03F7/20

    CPC分类号： H01L21/26586 ,  G03F7/40 ,  H01L29/6659

    摘要： A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature.

    摘要翻译： 形成抗蚀剂特征的方法包括在半导体本体上形成抗蚀剂层，并且选择性地暴露抗蚀剂层。 该方法还包括执行选择性曝光的抗蚀剂层的第一烘烤，以及使选择性曝光的抗蚀剂层显影以形成具有与其相关联的角边缘的抗蚀剂特征，从而暴露半导体本体的一部分。 然后进行显影的选择性曝光的抗蚀剂层的第二次烘烤，从而使抗蚀剂特征的拐角边缘四舍五入。

    Method of forming silicided gates using buried metal layers
    79.
    发明授权
    Method of forming silicided gates using buried metal layers 有权
    使用掩埋金属层形成硅化物栅的方法

    公开(公告)号：US07687396B2

    公开(公告)日：2010-03-30

    申请号：US11617897

    申请日：2006-12-29

    申请人： Steven Arthur Vitale ,  Shaofeng Yu

    发明人： Steven Arthur Vitale ,  Shaofeng Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28097

    摘要： A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

    摘要翻译： 一种方法包括在栅极电介质和衬底上形成包括多晶硅层，金属层和多晶硅层的栅极堆叠。 金属层被埋在栅极堆叠内，以在栅极的底部合金硅和金属。 然后蚀刻栅极堆叠以形成栅极。 然后进行硅化，以在栅极的底部形成硅化物。 可选地，第二金属层可以形成在栅叠层的顶部。 因此，在硅化期间，可以在栅极的顶部形成硅化物。

    METHOD OF FORMING SILICIDED GATES USING BURIED METAL LAYERS
    80.
    发明申请
    METHOD OF FORMING SILICIDED GATES USING BURIED METAL LAYERS 有权
    使用金属层形成硅胶门的方法

    公开(公告)号：US20080157258A1

    公开(公告)日：2008-07-03

    申请号：US11617897

    申请日：2006-12-29

    申请人： Steven Arthur Vitale ,  Shaofeng Yu

    发明人： Steven Arthur Vitale ,  Shaofeng Yu

    IPC分类号： H01L29/66 ,  H01L21/283

    CPC分类号： H01L21/28097

    摘要： A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

    摘要翻译： 一种方法包括在栅极电介质和衬底上形成包括多晶硅层，金属层和多晶硅层的栅极堆叠。 金属层被埋在栅极堆叠内，以在栅极的底部合金硅和金属。 然后蚀刻栅极堆叠以形成栅极。 然后进行硅化，以在栅极的底部形成硅化物。 可选地，第二金属层可以形成在栅叠层的顶部。 因此，在硅化期间，可以在栅极的顶部形成硅化物。