公开(公告)号：US20160163645A1

公开(公告)日：2016-06-09

申请号：US14563284

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. KAMINENI ,  Ruilong XIE

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7684 ,  H01L21/76844 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a lined bottom contact filled with conductive material. The structure further includes a layer of dielectric material surrounding sides of the lined bottom contact, a top contact on the bottom contact, the top contact having a partial liner only along sides thereof with an absence of the liner at a bottom thereof and being filled with the conductive material, and a layer of the dielectric material surrounding sides of the partially lined top contact. Fabrication of the bottom-liner free top contact includes providing a starting structure, the structure including a lined bottom contact filled with conductive material, being surrounded by a layer of dielectric material and having a planarized top surface. The method further includes creating a top layer of dielectric material above the planarized top surface, creating a layer of liner material above the top dielectric layer, creating a top contact opening to the bottom contact, lining the top contact opening with a liner material, removing the liner at a bottom of the top contact opening, exposing the bottom contact, while preserving a portion of the liner on the top dielectric layer sufficient to allow adhesion of a subsequent conductive material, and filling the contact opening with the conductive material.

Abstract translation: 半导体结构包括填充有导电材料的内衬底部接触。 所述结构还包括围绕所述衬里底部触点的侧面的介电材料层，所述底部触点上的顶部触点，所述顶部触点仅沿着其侧面具有部分衬垫，并且在其底部处不存在所述衬垫并且被填充 导电材料以及围绕部分衬里的顶部接触的侧面的电介质材料层。 底部衬垫自由顶部接触的制造包括提供起始结构，该结构包括填充有导电材料的内衬底部接触，被一层介电材料包围并具有平坦化的顶部表面。 该方法还包括在平坦化的顶部表面上方形成电介质材料的顶层，在顶部电介质层之上产生衬里材料层，形成到底部接触件的顶部接触开口，用衬里材料衬套顶部接触开口，去除 在顶部接触开口的底部处的衬垫暴露底部接触，同时保留顶部电介质层上的衬垫的一部分足以允许粘附随后的导电材料，并用导电材料填充接触开口。

公开(公告)号：US20160141489A1

公开(公告)日：2016-05-19

申请号：US14841997

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Xiuyu CAI ,  Seowoo NAM ,  Hyun-Jin CHO

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US20150357439A1

公开(公告)日：2015-12-10

申请号：US14295618

申请日：2014-06-04

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

公开(公告)号：US20150357243A1

公开(公告)日：2015-12-10

申请号：US14296818

申请日：2014-06-05

Applicant: STMICROELECTRONICS. INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAl ,  Ruilong XIE ,  Chun-chen YEH

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract translation: 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。

公开(公告)号：US20150228781A1

公开(公告)日：2015-08-13

申请号：US14175215

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu CAI ,  Qing LlU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

Abstract translation: 一种制造半导体器件的方法。 该方法可以包括在基板上形成翅片，每个翅片具有包括第一半导体材料的上翅片部分和包括电介质材料的下翅片部分。 该方法可以包括在每个下部翅片部分的侧壁中形成凹部以暴露相应的上部翅片部分的下表面，以及形成包围上翅片部分暴露的下表面的翅片的第二半导体层。 第二半导体层可以包括在第一半导体材料中产生应力的第二半导体材料。