公开(公告)号：US20150318169A1

公开(公告)日：2015-11-05

申请号：US14267634

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  David Paul Brunco

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片并使用硅烷（SiH 4），二氯硅烷（SiH 2 Cl 2），锗烷（GeH 4）和载气的组合进行外延沉积工艺以形成外延 散热片周围的半导体材料，其中在外延沉积工艺期间使用的二氯硅烷的流速等于硅烷和二氯硅烷的组合流速的10-90％。

公开(公告)号：US09165837B1

公开(公告)日：2015-10-20

申请号：US14525743

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Murat Kerem Akarvardar ,  Ajey P. Jacob ,  Steven Bentley

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/823431

Abstract: Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.

Abstract translation: 提供了在STI形成之前通过用H 2退火牺牲Si翅片来形成无缺陷异质外延替换翅片的方法。 实施例包括在基板上形成Si翅片; 用H2退火Si翅片; 在退火的Si翅片周围形成STI层; 退火STI层; 通过蚀刻去除退火的Si翅片的一部分，形成凹部; 在凹槽中形成替换翅片; 并使退火的STI层凹陷以暴露活性替换翅片。

公开(公告)号：US20150279973A1

公开(公告)日：2015-10-01

申请号：US14242472

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。

公开(公告)号：US20150014776A1

公开(公告)日：2015-01-15

申请号：US13937939

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract translation: 翅片场效应晶体管集成电路（FinFET IC）具有从半导体衬底延伸的多个鳍，其中在相邻鳍之间限定有槽。 第二电介质位于槽内，并且翅片的突出部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。