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    SEMICONDUCTOR DEVICES HAVING LATE-FORMED ISOLATION STRUCTURES
    71.
    发明申请
    SEMICONDUCTOR DEVICES HAVING LATE-FORMED ISOLATION STRUCTURES 有权

    公开(公告)号：US20210391323A1

    公开(公告)日：2021-12-16

    申请号：US16901417

    申请日：2020-06-15

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

    IPC: H01L27/088 ,  H01L21/8234

    Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

    NOVEL GATE STRUCTURE FOR AN LDMOS TRANSISTOR DEVICE
    73.
    发明申请
    NOVEL GATE STRUCTURE FOR AN LDMOS TRANSISTOR DEVICE 有权

    公开(公告)号：US20210351293A1

    公开(公告)日：2021-11-11

    申请号：US16870356

    申请日：2020-05-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Man Gu ,  Wang Zheng ,  Rong-Ting Liou ,  Haiting Wang ,  Wenjun Li

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A device is disclosed that includes a source region positioned in a first doped well region in a semiconductor substrate and a drain region positioned in a second doped well region in the substrate, wherein there is a well gap between the first doped well region and the second doped well region. The device also includes a gate structure that includes a first gate insulation layer positioned above an upper surface of the substrate, wherein the first gate insulation layer extends from a drain-side sidewall of the gate structure to a location above the well gap, and a second gate insulation layer having a first portion positioned above the upper surface of the substrate and a second portion positioned above the first gate insulation layer.

    Multi-level isolation structure
    74.
    发明授权
    Multi-level isolation structure 有权

    公开(公告)号：US11158633B1

    公开(公告)日：2021-10-26

    申请号：US16842075

    申请日：2020-04-07

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Haiting Wang ,  Sipeng Gu ,  Shesh Mani Pandey ,  Lixia Lei ,  Gregory Costrini

    IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/78

    Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

    Single fin structures
    76.
    发明授权
    Single fin structures 有权

    公开(公告)号：US11127842B2

    公开(公告)日：2021-09-21

    申请号：US16688267

    申请日：2019-11-19

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/45 ,  H01L21/285 ,  H01L29/417

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

    IC PRODUCTS FORMED ON A SUBSTRATE HAVING LOCALIZED REGIONS OF HIGH RESISTIVITY AND METHODS OF MAKING SUCH IC PRODUCTS
    79.
    发明申请
    IC PRODUCTS FORMED ON A SUBSTRATE HAVING LOCALIZED REGIONS OF HIGH RESISTIVITY AND METHODS OF MAKING SUCH IC PRODUCTS 有权

    公开(公告)号：US20210233934A1

    公开(公告)日：2021-07-29

    申请号：US16774087

    申请日：2020-01-28

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

    IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

    Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

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