公开(公告)号：US11424349B1

公开(公告)日：2022-08-23

申请号：US17177490

申请日：2021-02-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: A lateral bipolar junction transistor (BJT) device includes: an emitter region, a collector region, and a base region, the base region positioned between and laterally separating the emitter region and the collector region, the base region including an intrinsic base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating a lower surface of the intrinsic base region from the semiconductor substrate.

公开(公告)号：US11329158B2

公开(公告)日：2022-05-10

申请号：US16843421

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Halting Wang ,  Judson R. Holt ,  Sipeng Gu

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.

公开(公告)号：US11049955B2

公开(公告)日：2021-06-29

申请号：US16727453

申请日：2019-12-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.

公开(公告)号：US12009412B2

公开(公告)日：2024-06-11

申请号：US17549013

申请日：2021-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/732 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/66234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

公开(公告)号：US11990535B2

公开(公告)日：2024-05-21

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/02532 ,  H01L21/2251 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US11977258B1

公开(公告)日：2024-05-07

申请号：US18148029

申请日：2022-12-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Laura J. Silverstein ,  Steven M. Shank ,  Judson R. Holt ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/02 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/02042 ,  G02B6/02333 ,  G02B2006/121

Abstract: Disclosed are a structure with a substrate-embedded waveguide and a method of forming the structure. The waveguide includes cladding material lining a trench in a substrate, a core in the trench on the cladding material, and at least one cavity within the core. Each cavity extends from one end of the core toward the opposite end and contains a low refractive index material or is under vacuum so the waveguide is an arrow waveguide. An insulator layer is on the substrate and extends laterally over the waveguide and a semiconductor layer is on the insulator layer. Additionally, depending upon the embodiment, an additional waveguide can be aligned above the substrate-embedded waveguide either on the isolation region or on a waveguide extender that extends at least partially through the isolation region and the insulator layer to the waveguide.

公开(公告)号：US11907685B2

公开(公告)日：2024-02-20

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: H04L9/32 ,  G06F7/58 ,  H04L9/08 ,  G06F21/00 ,  G06F21/73 ,  G06F21/72 ,  G06F21/76 ,  H01L21/02 ,  H01L27/088

CPC classification number: G06F7/588 ,  G06F21/00 ,  G06F21/72 ,  G06F21/73 ,  G06F21/76 ,  H01L21/02233 ,  H04L9/0866 ,  H04L9/3278 ,  H01L27/088 ,  H04L2209/12

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US11888031B2

公开(公告)日：2024-01-30

申请号：US17537564

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737 ,  H01L29/735

CPC classification number: H01L29/1008 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737

Abstract: In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.

公开(公告)号：US11855197B2

公开(公告)日：2023-12-26

申请号：US17580127

申请日：2022-01-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Alexander M. Derrickson ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

公开(公告)号：US11799021B2

公开(公告)日：2023-10-24

申请号：US17450842

申请日：2021-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.