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公开(公告)号：US5827440A
公开(公告)日：1998-10-27
申请号：US711940
申请日：1996-09-04
CPC分类号： B29C45/14073 , B29C33/123 , B29C33/14 , B29C2045/14081 , B29L2031/3406 , B29L2031/752
摘要： A temperature sensor forming method and forming die are provided which perform insert-forming of a temperature sensor with a minimum of processes and in a short time. The temperature sensor formed has a temperature sensing element 1 arranged in a predetermined position inside a resin case 2. The process does not leave traces of pins that would allow water to penetrate the interior of the case. The process comprises a first step of supporting the temperature sensing element 1 with first and second slide blocks 6c and 6g. The process comprises a second step of injecting a molten forming resin 2a into a forming die 6 and retracting the first slide block 6c by injection pressure while the temperature sensing element 1 is being supported by the second slide block 6g. The process comprises a third step of retracting the second slide block 6g while injecting the molten forming resin 2a into the forming die 6. The receiving area S1 of the first slide block 6c is larger than the receiving area S2 of the second slide block 6g.
摘要翻译： 提供一种温度传感器形成方法和成形模具，其以最少的工艺和在短时间内进行温度传感器的插入成形。 形成的温度传感器具有布置在树脂壳体2内的预定位置的温度感测元件1.该过程不留下允许水渗透到壳体内部的销的痕迹。 该方法包括用第一和第二滑动块6c和6g支撑温度感测元件1的第一步骤。 该方法包括将熔融成型树脂2a注入成形模具6中并且在温度感测元件1被第二滑块6g支撑的同时通过注射压力缩回第一滑块6c的第二步骤。 该方法包括在将熔融成型树脂2a注入成形模具6的同时将第二滑块6g缩回的第三步骤。第一滑块6c的接收区域S1大于第二滑块6g的接收区域S2。
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72.发明授权
公开(公告)号：US5812445A
公开(公告)日：1998-09-22
申请号：US825063
申请日：1997-03-27
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C11/412 , G11C11/417 , G11C11/419 , G11C7/00
CPC分类号： G11C11/417 , G11C11/412 , G11C11/419
摘要： A memory cell is formed by flip-flop connection of a load transistor pair of a first load transistor and a second load transistor and a drive transistor pair of a first drive transistor and a second drive transistor. A first switch which is controlled by a wordline and a second switch which is activated only at the time of the write operation are connected in series to a first memory node. The second switch is serially coupled between the first memory node and the first drive transistor. An electric current is injected from a sense amplifier into a bitline pair selected at the time of the read operation, to detect an impedance which varies with the signal potential at the first memory node.
摘要翻译： 通过第一负载晶体管和第二负载晶体管的负载晶体管对和第一驱动晶体管和第二驱动晶体管的驱动晶体管对的触发器连接来形成存储单元。 由字线控制的第一开关和仅在写操作时被激活的第二开关被串联连接到第一存储器节点。 第二开关串联耦合在第一存储器节点和第一驱动晶体管之间。 从读出放大器将电流注入到在读取操作时选择的位线对，以检测随着第一存储节点处的信号电位而变化的阻抗。
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公开(公告)号：US5642314A
公开(公告)日：1997-06-24
申请号：US706196
申请日：1996-08-30
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C5/14 , G11C7/10 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C7/00
CPC分类号： G11C5/143 , G11C11/4091 , G11C11/4096 , G11C7/1048
摘要： A second power supply line is connected to a first power supply line via an N-MOS transistor and has a second potential (Vcc-Vt). The second power supply line is grounded to a ground line via one of P-MOS transistors of a clamp circuit, one of N-MOS transistors of a decode switch, an N-MOS sense amplifier, and a common source line of sense amplifiers. Accordingly, even when a power supply potential negatively bumps, a ground potential flows from the second power supply line through a current path thus formed, and the potential of the second power supply line can follow the negative bump. Since the transistors forming the clamp circuit are of the P-MOS type, the data lines are electrically connected to the second power supply line, so that the data lines can follow the negative bump of the first power supply line. Accordingly, it is possible to provide a data line precharging system which can follow the negative bump of the power supply without deteriorating the sensitivity of the amplifier of the voltage detecting type.
摘要翻译： 第二电源线经由N-MOS晶体管连接到第一电源线，并具有第二电位（Vcc-Vt）。 第二电源线通过钳位电路的P-MOS晶体管中的一个接地，解码开关的N-MOS晶体管，N-MOS读出放大器和读出放大器的公共源极线之一。 因此，即使当电源电势负凸时，接地电位从第二电源线通过如此形成的电流路径流动，并且第二电源线的电位可以跟随负凸起。 由于形成钳位电路的晶体管为P-MOS型，所以数据线与第二电源线电连接，使得数据线可以跟随第一电源线的负凸。 因此，可以提供可以跟随电源的负凸起的数据线预充电系统，而不会降低电压检测类型的放大器的灵敏度。
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74.发明授权
公开(公告)号：US5581506A
公开(公告)日：1996-12-03
申请号：US382530
申请日：1995-02-02
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C7/10 , H03K19/0185 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , H03K19/018521
摘要： During a period corresponding to the former half of one cycle of a clock signal, a capacitor is charged to an intermediate potential between the respective precharged potentials of two level-shifters. Subsequently, during a period corresponding to the latter half of one cycle of the clock signal, the capacitor is connected to that one of the output nodes which shifts to a lower potential in the level-shifter on the upper stage, while a power source line is connected to the other output node which shifts to a higher potential. On the other hand, the capacitor is also connected to that one of the output nodes which shifts to the higher potential in the level-shifter on the lower stage, while the ground line is connected to the other output node which shifts to the lower potential. Consequently, there can be provided a semiconductor integrated circuit free from power dissipation that might have been caused by an internal power-source circuit. The semiconductor integrated circuit enables data transfer with a small amplitude and consumes an extremely small amount of current even when multi-bit data lines operate in parallel.
摘要翻译： 在对应于时钟信号的一个周期的前半个周期期间，电容器被充电到两个电平转换器的各个预充电电位之间的中间电位。 随后，在对应于时钟信号的一个周期的后半段的时间段期间，电容器连接到在上级的电平转换器中转移到较低电位的输出节点中的一个，而电源线 连接到另一个输出节点，转换到更高的电位。 另一方面，电容器也连接到输出节点中的一个，该输出节点转移到下级电平移位器中的较高电位，而地线连接到另一输出节点，该输出节点转移到较低电位 。 因此，可以提供可能由内部电源电路引起的没有功率耗散的半导体集成电路。 即使在多位数据线并行运行时，半导体集成电路也能够以小幅度进行数据传输，并且消耗极小的电流。
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公开(公告)号：US5257271A
公开(公告)日：1993-10-26
申请号：US939406
申请日：1992-09-01
申请人： Roger Lagadec , Keisuke Sekiguchi , Hiroyuki Yamauchi , Masaru Tezuka , Satoru Tobita , Yoichiro Sako , Hiroyuki Hara, deceased
发明人： Roger Lagadec , Keisuke Sekiguchi , Hiroyuki Yamauchi , Masaru Tezuka , Satoru Tobita , Yoichiro Sako , Hiroyuki Hara, deceased
CPC分类号： H03M13/2764 , G11B20/1809
摘要： In a sampled data transmitting apparatus in which the sampled data to be transmitted are divided into odd-numbered samples and even-numbered samples and arranged in different rows of a two-dimensional data array, and in which error correction codes are annexed to each row and to each column of the two-dimensional data array, the row arraying sequence in one of the odd-numbered or even-numbered rows is caused to differ from the row arraying sequence in the other of the odd-numbered or even-numbered rows so that odd-numbered data and even-numbered data continuous with the odd-numbered data are not arranged in one row. In this manner, even when error correction becomes impossible by the error correcting code for one row, interpolation remains feasible because there exist no odd-numbered data or even-numbered data contiguous to each other in the row.
摘要翻译： 在采样数据发送装置中，将要发送的采样数据划分为奇数样本和偶数样本，并排列在二维数据阵列的不同行中，其中纠错码附于每行 并且对于二维数据阵列的每列，使奇数或偶数行之一中的行排列顺序与奇数行或偶数行中的另一行中的行排列顺序不同 使得与奇数数据连续的奇数数据和偶数数据不排列在一行中。 以这种方式，即使通过一行的纠错码不可能进行纠错，因为在该行中不存在彼此邻接的奇数数据或偶数数据，因此内插仍然是可行的。
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公开(公告)号：US5229964A
公开(公告)日：1993-07-20
申请号：US617873
申请日：1990-11-26
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C11/413 , C21C5/40 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/419 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4096 , G11C11/4091
摘要： A circuit for reading and writing data to/from memory cells of a DRAM, based upon sense amplifiers formed of N-type and P-type FETs for each pair of bit lines of the DRAM and column switches formed of FETs for transferring data potentials to/from the bit line pairs, in which the current drive capability of the column switches is increased relative to the sense amplifiers during each write cycle and the current drive capability of the sense amplifiers is increased relative to that of the column switches during each read cycle, thereby ensuring satisfactory read and write operation even for a very large-scale DRAM operating with a low value of supply voltage.
摘要翻译： 基于用于DRAM的每对位线的N型和P型FET形成的读出放大器和用于将数据电位传送到FET的由FET形成的列开关的用于从DRAM的存储单元读取/写入数据的电路 来自位线对，其中列开关的当前驱动能力在每个写周期期间相对于读出放大器增加，并且读出放大器的当前驱动能力相对于每个读周期中的列开关的驱动能力增加 ，从而即使对于具有低电源电压的非常大规模的DRAM进行操作，也能确保令人满意的读写操作。
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公开(公告)号：US5051957A
公开(公告)日：1991-09-24
申请号：US462538
申请日：1990-01-03
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C7/06
摘要： A sense amplifier circuit for a semiconductor memory includes a flip-flop coupled to a pair of bit lines connected to memory cells, for amplifying a differential read voltage produced between the bit lines, and at least two switches for applying respectively different levels of drive voltage to a common node of the flip-flop. The switches are controlled such as to apply a relatively high value of drive voltage to the common node when a read operation is initiated, to thereby initially provide a high charging current to the bit line capacitance, and thereafter supply a lower value of drive voltage to thereby ensure reliability of the memory cell oxide film.
摘要翻译： 用于半导体存储器的读出放大器电路包括耦合到连接到存储器单元的一对位线的触发器，用于放大在位线之间产生的差分读取电压，以及至少两个开关，分别施加不同级别的驱动电压 到触发器的公共节点。 控制这些开关，以便在开始读取操作时向公共节点施加相对较高的驱动电压值，从而首先向位线电容提供高充电电流，然后将较低的驱动电压值提供给 从而确保记忆单元氧化膜的可靠性。
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公开(公告)号：US4920517A
公开(公告)日：1990-04-24
申请号：US182895
申请日：1988-04-18
IPC分类号： G11C11/4097
CPC分类号： G11C11/4097
摘要： A dynamic random access memory which includes a memory cell array, sense amplifiers disposed at both side of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines are coupled to data busses through middle amplifiers. By use of such memory architecture, higher integration of DRAM can be realized. Also, handling of super large bit data more than 1024 bit becomes possible.
摘要翻译： 一种动态随机存取存储器，其包括存储单元阵列，设置在存储单元阵列两侧的读出放大器以及耦合到读出放大器的子位线。 子位线通过中间放大器耦合到数据总线。 通过使用这种存储器架构，可以实现DRAM的更高集成度。 而且，超大于1024位的超大位数据的处理成为可能。
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公开(公告)号：US4904888A
公开(公告)日：1990-02-27
申请号：US253216
申请日：1988-10-03
申请人： Hiroyuki Yamauchi , Toshio Yamada
发明人： Hiroyuki Yamauchi , Toshio Yamada
IPC分类号： G11C11/409 , G01R19/00 , G11C7/06 , H03K17/10 , H03K17/14
CPC分类号： G11C7/065 , H03K17/102 , H03K17/145
摘要： In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.
摘要翻译： 为了提高读出放大器电路的灵敏度，构成读出放大器电路的晶体管对中的每一个由以偶数个级并联连接的晶体管形成，因此读出放大器电路由具有极高的晶体管对 平衡特性，消除晶体管对的电流 - 电压特性的不对称性为零。
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公开(公告)号：US07749950B2
公开(公告)日：2010-07-06
申请号：US11480410
申请日：2006-07-05
CPC分类号： C09D4/00 , C04B14/062 , C04B18/146 , C04B41/009 , C04B41/5089 , C04B41/52 , C04B41/68 , C04B41/71 , C04B2111/2038 , Y02W30/94 , Y02W30/97 , Y10T442/2279 , C04B41/46 , C04B2103/408 , C04B41/463 , C04B41/4876 , C04B41/502 , C04B41/483 , C04B41/522 , C04B18/26 , C04B28/18
摘要： An object of the present invention is to provide a durable excellent stain-proofing property to the surface of a coating formed on a substrate surface of a building board without deteriorating the surface of the coating. The present invention also, provides a stain-proofing agent containing silica fine particles, an aqueous solvent and, as a stain-proofing improver, an alkali metal compound and/or an alkaline earth metal compound and/or a phosphorus compound and/or a clay mineral. The present invention also provides a building board having an excellent stain-proofing property prepared by applying a coating composition onto the surface of a substrate to form a coat, and then applying a stain-proofing agent onto the coat while the coat is in an unhardened state or applying a stain-proofing agent onto the coat after subjecting the coat to a roughening treatment to enhance the adhesion of the stain-proofing layer to the coat.
摘要翻译： 本发明的目的是提供一种耐久性优异的防污染性能，而不会使涂层的表面劣化，从而在建筑板的基板表面上形成的涂层的表面具有良好的耐污染性。 本发明还提供了含有二氧化硅微粒，水性溶剂和作为防污改良剂的碱金属化合物和/或碱土金属化合物和/或磷化合物和/或 粘土矿物。 本发明还提供了一种建筑板，其具有通过将涂料组合物涂布在基材表面上以形成涂层而制备的优异的防污性，然后在涂层处于未硬化的同时将防污剂施加到涂层上 在使涂层进行粗糙化处理以增强防污层与涂层的粘附性之后，将涂布防污剂施加到涂层上。
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