公开(公告)号：US20110095971A1

公开(公告)日：2011-04-28

申请号：US12638959

申请日：2009-12-15

Applicant: Hsiang-Lin Lin ,  Chia-Hsun Tu ,  Chih-Jen Hu ,  Wei-Ming Huang

Inventor： Hsiang-Lin Lin ,  Chia-Hsun Tu ,  Chih-Jen Hu ,  Wei-Ming Huang

IPC: G02F1/167 ,  G09G3/34

CPC classification number: G09G3/3446 ,  G02F1/167 ,  G02F2001/1676

Abstract: An electrophoresis display pixel including an electrophoresis display film, a substrate, a first active device, a second active device, a first electrode, and a second electrode is provided. The substrate is disposed on the electrophoresis display film, and the substrate has a transparent region and a non-transparent region. The first active device and the second active device are disposed on the substrate and located in the non-transparent region. The first electrode is disposed on the substrate, located in the transparent region, and electrically connected to the first active device. The second electrode is disposed on the substrate, located in the non-transparent region, and electrically connected to the second active device. A light passes through the transparent region and enters the electrophoresis display film to be displayed. A display apparatus including the abovementioned electrophoresis display pixel is also provided.

Abstract translation: 提供了包括电泳显示膜，基板，第一有源器件，第二有源器件，第一电极和第二电极的电泳显示像素。 基板设置在电泳显示膜上，基板具有透明区域和不透明区域。 第一有源器件和第二有源器件设置在衬底上并且位于不透明区域中。 第一电极设置在基板上，位于透明区域中，并电连接到第一有源器件。 第二电极设置在基板上，位于非透明区域中，并电连接到第二有源器件。 光通过透明区域并进入电泳显示膜以显示。 还提供了包括上述电泳显示像素的显示装置。

公开(公告)号：US07872262B2

公开(公告)日：2011-01-18

申请号：US12700678

申请日：2010-02-04

Applicant: Hsiang-Lin Lin ,  Sung-Kao Liu

Inventor： Hsiang-Lin Lin ,  Sung-Kao Liu

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC classification number: G02F1/136227 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2001/136218

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

公开(公告)号：US07842954B2

公开(公告)日：2010-11-30

申请号：US12775493

申请日：2010-05-07

Applicant: Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

Inventor： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC: H01L33/00

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

Abstract translation: 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US20090033815A1

公开(公告)日：2009-02-05

申请号：US11941534

申请日：2007-11-16

Applicant: Hsiang-Lin Lin ,  Seok-Lyul Lee ,  Tun-Chun Yang

Inventor： Hsiang-Lin Lin ,  Seok-Lyul Lee ,  Tun-Chun Yang

IPC: G02F1/1343 ,  H01L27/088 ,  H01L21/84

CPC classification number: G02F1/133707 ,  G02F1/134336 ,  G02F2201/40 ,  H01L27/124 ,  H01L29/42384

Abstract: A pixel structure is provided. The pixel structure comprises a lower substrate with a transistor and pixel area; a first patterned conductive layer, which has a data line and a gate within the transistor area that is disposed on the lower substrate; a patterned insulator layer covering the first patterned conductive layer; an active layer disposed on the patterned insulator layer above the gate; a second patterned conductive layer with a gate line disposed on the patterned insulator layer, source and drain, wherein the source and the drain are disposed on the active layer; a pixel electrode disposed on the patterned insulator layer and electrically connected to the drain; a patterned passivation layer disposed on the patterned insulator layer, gate line, source, drain and pixel electrode; and a third patterned conductive layer, which has a data line connecting electrode, a gate line connecting electrode, at least one alignment electrode and a common electrode. The data line is electrically connected to the source through the data line connecting electrode; the gate line is electrically connected to the gate through the gate line connecting electrode; the alignment electrode is electrically connected to the pixel electrode; and a portion of the common electrode is disposed above the data line.

Abstract translation: 提供像素结构。 像素结构包括具有晶体管和像素区域的下基板; 第一图案化导电层，其具有设置在下基板上的晶体管区域内的数据线和栅极; 覆盖所述第一图案化导电层的图案化绝缘体层; 设置在栅极上方的图案化绝缘体层上的有源层; 第二图案化导电层，其栅极线设置在图案化绝缘体层，源极和漏极上，其中源极和漏极设置在有源层上; 设置在所述图案化绝缘体层上并电连接到所述漏极的像素电极; 布置在图案化绝缘体层，栅极线，源极，漏极和像素电极上的图案化钝化层; 以及具有数据线连接电极，栅极线连接电极，至少一个取向电极和公共电极的第三图案化导电层。 数据线通过数据线连接电极与源极电连接; 栅极线通过栅极线连接电极电连接到栅极; 对准电极电连接到像素电极; 并且公共电极的一部分设置在数据线的上方。

公开(公告)号：US20080158703A1

公开(公告)日：2008-07-03

申请号：US11933421

申请日：2007-11-01

Applicant: Chun-Chieh Tsao ,  Shu-Chin Lee ,  Hsiang-Lin Lin

Inventor： Chun-Chieh Tsao ,  Shu-Chin Lee ,  Hsiang-Lin Lin

IPC: G02B5/20 ,  G03F1/00

CPC classification number: G02B5/201 ,  G02B5/223 ,  G02F1/133516

Abstract: A manufacturing method of a color filter comprising the following steps is provided. At first, a transparent substrate is provided. Next, a black matrix is formed on the transparent substrate to define a plurality of pixel areas on the transparent substrate. Then, an isolation layer is formed and patterned on the black matrix and then Red/Green/Blue color filter inks are filled into each of the pixel areas separately by inkjet printing. After that, the color filter inks are dried to form color filter units and optionally the isolation layer can further be patterned to form plenty of photo spacers on the black matrix. The isolation layers prevented the color filter inks from spilling out of the pixel areas and color mixing problems during color filter inkjet fabrication. Besides, it is characterized that the color filter units can be formed with even thickness.

Abstract translation: 提供了一种包括以下步骤的滤色器的制造方法。 首先，提供透明基板。 接下来，在透明基板上形成黑矩阵，以在透明基板上限定多个像素区域。 然后，在黑矩阵上形成并图案化隔离层，然后通过喷墨打印将红/绿/蓝滤色器墨水分别填充到每个像素区域中。 之后，将滤色器油墨干燥以形成滤色器单元，并且任选地隔离层可进一步图案化以在黑色矩阵上形成大量的光隔离物。 隔离层防止滤色器墨水在滤色器喷墨制造期间溢出像素区域和混色问题。 此外，其特征在于可以形成均匀厚度的滤色器单元。

公开(公告)号：US20070236414A1

公开(公告)日：2007-10-11

申请号：US11382059

申请日：2006-05-08

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: G09G3/28

CPC classification number: G02F1/134309 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/13606

Abstract: A liquid crystal display includes: a substrate; a plurality of pixel electrodes formed on the substrate and arranged corresponding to a pixel array; a first data line and a second data line formed on the substrate; a plurality of scan lines formed on the substrate, in which the scan lines cross the first data line and the second data line; a first branch electrode electrically connects a pixel electrode and partially overlaps the first data line; and a second branch electrode electrically connects the pixel electrode and partially overlaps the second data line, in which the first branch electrode and the second branch electrode are disposed opposite to the pixel electrode.

Abstract translation: 液晶显示器包括：基板; 多个像素电极，其形成在所述基板上并且对应于像素阵列排列; 形成在所述基板上的第一数据线和第二数据线; 形成在所述基板上的扫描线，其中所述扫描线与所述第一数据线和所述第二数据线交叉; 第一分支电极电连接像素电极并与第一数据线部分重叠; 并且第二分支电极电连接像素电极，并且与第二数据线部分重叠，其中第一分支电极和第二分支电极与像素电极相对设置。

公开(公告)号：US20070171320A1

公开(公告)日：2007-07-26

申请号：US11382712

申请日：2006-05-11

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: G02F1/136

CPC classification number: G02F1/136286 ,  G02F2001/13606 ,  G02F2001/136218 ,  G02F2201/40

Abstract: A pixel structure of a liquid crystal display (LCD) includes a scan line, a data line and a thin film transistor (TFT) disposed on the substrate. The TFT has a source electrically connected to the date line and a gate electrically connected to the scan line. A shielding electrode disposes on the substrate, wherein the same metal layer makes the shielding electrode, the source and the drain. Furthermore, the data line makes at least two different patterned metal, layers which are not formed simultaneously and the patterned metal layers are electrically connected to each other. A pixel electrode covers the part of the shielding electrode and electrically connects to the drain.

Abstract translation: 液晶显示器（LCD）的像素结构包括设置在基板上的扫描线，数据线和薄膜晶体管（TFT）。 TFT具有电连接到日期线的源极和电连接到扫描线的栅极。 屏蔽电极配置在基板上，其中相同的金属层形成屏蔽电极，源极和漏极。 此外，数据线使得至少两个不同的图案化金属层不同时形成，并且图案化的金属层彼此电连接。 像素电极覆盖屏蔽电极的一部分并电连接到漏极。

公开(公告)号：US6033589A

公开(公告)日：2000-03-07

申请号：US941713

申请日：1997-09-30

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: B05D1/00 ,  H01L21/00 ,  C09D5/20

CPC classification number: H01L21/6715 ,  B05D1/005 ,  H01L21/67051

Abstract: The present invention discloses a method for depositing a coating layer on an article without edge bead formation by integrating the steps of an edge bead rinsing process with a coating spin-out process such that an edge portion of the wafer can be efficiently cleaned with a cleaning solvent when the coating material is still in its liquid state. While the present invention method can be applied to any coating materials and to any coated substrate, it is particularly suitable for cleaning a spin-on-glass material from a semiconductor wafer such that the wafer edge is not coated with a SOG material and thus particulate contamination caused by cracked SOG from the wafer edge can be avoided.

Abstract translation: 本发明公开了一种用于在没有边缘珠形成的物品上沉积涂层的方法，该方法是通过将边缘珠清洗工艺与涂层旋转工艺相结合的步骤整合在一起，使得可以用清洁剂有效地清洁晶片的边缘部分 当涂料仍处于其液态时，溶剂即可。 虽然本发明的方法可以应用于任何涂层材料和任何涂覆的基底，但是特别适用于从半导体晶片清洗旋涂玻璃材料，使得晶片边缘未涂覆有SOG材料，因此颗粒 可以避免由晶片边缘破裂的SOG引起的污染。

公开(公告)号：US5994219A

公开(公告)日：1999-11-30

申请号：US90498

申请日：1998-06-04

Applicant: Hsiang-Lin Lin ,  Han-Chung Chen

Inventor： Hsiang-Lin Lin ,  Han-Chung Chen

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/441

CPC classification number: H01L21/28512 ,  H01L21/76838

Abstract: A new method of metal deposition with reduced metal residue after metal etching by cooling the wafer before metal deposition is described. A first patterned conducting layer is provided overlying a dielectric layer on the surface of a semiconductor substrate. The wafer is cooled to a temperature of less than about 20.degree. C. Thereafter, a metal layer is deposited overlying the first patterned conducting layer. The metal layer is etched away where it is not covered by a mask to complete formation of the metal line. Cooling of the wafer before metal deposition decreases the metal residue found after metal etching.

Abstract translation: 描述了在金属沉积之前通过冷却晶片在金属蚀刻之后金属沉积减少的新方法。 第一图案化导电层设置在半导体衬底的表面上覆盖介电层。 将晶片冷却至低于约20℃的温度。此后，沉积覆盖第一图案化导电层的金属层。 金属层被蚀刻掉，其未被掩模覆盖以完成金属线的形成。 在金属沉积之前，晶片的冷却减少金属蚀刻后发现的金属残留。

公开(公告)号：US08420463B2

公开(公告)日：2013-04-16

申请号：US13163774

申请日：2011-06-20

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Chin-Yueh Liao

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Chin-Yueh Liao

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/118 ,  H01L23/52

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/1288

Abstract: A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.

Abstract translation: 像素结构包括扫描线，数据线，有源元件，第一钝化层，第二钝化层和像素电极。 数据线包括第一数据金属段和第二数据金属层。 有源元件包括栅电极，绝缘层，沟道层，源极和漏极。 沟道层位于栅电极上方的绝缘层上。 源极和漏极位于沟道层上。 源耦合到数据线。 第一钝化层和第二钝化层覆盖有源元件并形成第一接触孔以暴露漏极的一部分。 第二钝化层覆盖漏极的一部分边缘。 像素电极跨越第二钝化层设置并且经由第一接触孔耦合到漏极。