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    Phase change memory cell with large electrode contact area
    71.
    发明授权
    Phase change memory cell with large electrode contact area 有权
    具有大电极接触面积的相变存储单元

    公开(公告)号：US09166161B2

    公开(公告)日：2015-10-20

    申请号：US14490990

    申请日：2014-09-19

    Applicant: International Business Machines Corporation

    Inventor： Matthew J. BrightSky ,  Chung H. Lam ,  Jing Li ,  Alejandro G. Schrott ,  Norma E. Sosa Cortes

    IPC: H01L45/00

    CPC classification number: H01L45/1253 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. A second non-conductive layer is deposited above the first non-conductive layer. A second well is defined by the second non-conductive layer and positioned directly above the first well. A second electrically conductive liner lines at least one wall of the second well such that the second electrically conductive liner is not in physical contact with the first electrically conductive liner. Furthermore, the phase change material is deposited in the second well.

    Abstract translation: 相变存储单元及相变存储单元的制造方法。 相变存储单元包括底电极和第一非导电层。 第一非导电层限定第一阱，第一导电衬垫在第一阱中排列，并且第一阱在相变存储单元中填充有相变材料。 第二非导电层沉积在第一非导电层上方。 第二个阱由第二个非导电层限定，并直接位于第一个井的上方。 第二导电衬垫衬有第二阱的至少一个壁，使得第二导电衬垫不与第一导电衬垫物理接触。 此外，相变材料沉积在第二阱中。

    SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
    73.
    发明申请
    SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES 审中-公开
    用于半导体器件特征的单掩模间距技术

    公开(公告)号：US20140252556A1

    公开(公告)日：2014-09-11

    申请号：US13786520

    申请日：2013-03-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chung H. Lam ,  Jing Li

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating semiconductor features. The method includes forming a first layer over a substrate. Forming a plurality of first holes in the first layer. The first layer includes sidewalls separating at least a portion of each first hole. The first holes include overlapping holes that are not separated by the sidewalls. Forming a plurality of spacers on the substrate and first layer. The spacers include spacer sidewalls separating adjacent overlapping holes. Etching exposed portions of the substrate to form a plurality of second holes.

    Abstract translation: 一种制造半导体特征的方法。 该方法包括在衬底上形成第一层。 在第一层中形成多个第一孔。 第一层包括分隔每个第一孔的至少一部分的侧壁。 第一孔包括不被侧壁分隔的重叠孔。 在基板和第一层上形成多个间隔物。 间隔件包括分隔相邻重叠孔的间隔壁。 蚀刻基板的暴露部分以形成多个第二孔。

    INFERENCE MODEL ON RESTRAINED GPU MEMORY
    75.
    发明公开
    INFERENCE MODEL ON RESTRAINED GPU MEMORY 审中-公开

    公开(公告)号：US20230274165A1

    公开(公告)日：2023-08-31

    申请号：US17652714

    申请日：2022-02-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Guang Han Sui ,  Bin Xu ,  Jing Li ,  QING XU ,  Lin Dong

    IPC: G06N5/04 ,  G06F9/50

    CPC classification number: G06N5/04 ,  G06F9/5011

    Abstract: A method, a computer program product, and a computer system run an inference model with a graphical processing unit (GPU) having a restrained resource. The method includes receiving an input to run a sequential inference process comprising a plurality of layers. The method comprises determining inference model information. The method comprises determining a count (M) of the layers for each step to load and run based on the inference model information. The method comprises determining allocations in the available GPU memory configured for data associated with the M layers, a step input and a step output, and intermediate information. The method comprises loading and running the M layers using the step input to calculate the step output. The method comprises generating the intermediate information for the step output for a subsequent step to utilize the step output as a further step input in the subsequent step.

    MATCHING CRYPTOGRAPHIC COMPUTING RESOURCES TO THE PREDICTED REQUIREMENTS FOR DECRYPTING ENCRYPTED COMMUNICATIONS
    77.
    发明申请
    MATCHING CRYPTOGRAPHIC COMPUTING RESOURCES TO THE PREDICTED REQUIREMENTS FOR DECRYPTING ENCRYPTED COMMUNICATIONS 有权

    公开(公告)号：US20230068521A1

    公开(公告)日：2023-03-02

    申请号：US17411383

    申请日：2021-08-25

    Applicant: International Business Machines Corporation

    Inventor： Heng Wang ,  Wan Yue Chen ,  Chen Guang Liu ,  Jing Li ,  Xiao Ling Chen ,  Peng Hui Jiang

    IPC: G06F21/60 ,  G06N20/00

    Abstract: Embodiments of the invention include a computer-implemented method that uses a processor to access cryptographic-function constraints associated with an encrypted message. Based on a determination that the cryptographic-function constraints do not include mandatory cryptographic computing resource requirements, first resource-scaling operations are performed that include an analysis of cryptographic metrics associated with a processor. The cryptographic metrics include information associated with the encrypted message, along with performance measurements of cryptographic functions performed by the processor. The cryptographic-function constraints and results of the analysis of the cryptographic metrics are used to determine cryptographic processing requirements of the encrypted message; and match the cryptographic processing requirements to selected ones of a set of cryptographic computing resources to identify a customized set of cryptographic computing resources matched to cryptographic processing requirements of the encrypted message. The customized set of cryptographic computing resources is used to perform customized cryptographic functions on the encrypted message.

    Detecting deviations between event log and process model
    80.
    发明授权
    Detecting deviations between event log and process model 有权

    公开(公告)号：US10467539B2

    公开(公告)日：2019-11-05

    申请号：US14748837

    申请日：2015-06-24

    Applicant: International Business Machines Corporation

    Inventor： Jing Li ,  Xiang Li ,  Haifeng Liu ,  Guo Tong Xie ,  Yi Qin Yu ,  Shi Lei Zhang

    IPC: G06N7/00

    Abstract: A method for detecting deviations between an event log and a process model includes converting the process model into a probability process model, the probability process model comprising multiple nodes in multiple hierarchies and probability distribution associated with the multiple nodes, a leaf node among the multiple nodes corresponding to an activity in the process model; detecting differences between at least one event sequence contained in the event log and the probability process model according to a correspondence relationship; and identifying the differences as the deviations in response to the differences exceeding a predefined threshold; wherein the correspondence relationship describes a correspondence relationship between an event in one event sequence of the at least one event sequence and a leaf node in the probability process model.

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