-
公开(公告)号：US09196829B2
公开(公告)日：2015-11-24
申请号：US13833139
申请日：2013-03-15
CPC分类号： H01L45/126 , H01L45/04 , H01L45/1226 , H01L45/144
摘要： Defining an active region of a phase change memory (PCM) cell including depositing a first layer of material having a first chemical composition. A second layer of material having a second chemical composition is deposited on top of the first layer of material. An electrical current pulse is applied to locally heat a region of the first layer of material and the second layer of material to cause at least one of an inter-diffusion and a liquid mixing of the first layer of material and the second layer of material. This results in in the PCM cell containing a self-aligned region that includes a phase change material that is a mixture of the first chemical composition and the second chemical composition.
摘要翻译： 定义相变存储器（PCM）单元的有源区，包括沉积具有第一化学成分的第一材料层。 具有第二化学成分的第二层材料沉积在第一层材料的顶部上。 施加电流脉冲以局部加热第一材料层和第二材料层的区域以引起第一材料层和第二材料层的相互扩散和液体混合中的至少一个。 这导致包含自对准区域的PCM单元包括作为第一化学组成和第二化学组成的混合物的相变材料。
-
公开(公告)号：US20150309941A1
公开(公告)日：2015-10-29
申请号：US14264463
申请日：2014-04-29
IPC分类号： G06F12/10
CPC分类号： G11C11/418 , G06F12/10
摘要： An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines.
摘要翻译： 本发明的一个方面是用于在存储器件中提供PreSET区域的方法，其中PreSET区域包括已经被PreSET存储器件的一行或多行; 通过写入PreSET区域而不是写入到存储器件的位置线来对存储器件的一个或多个不合适的行执行写入操作; 以及在所述间接表中存储所述存储器设备的相应多个逻辑页面中的每一个到所述存储器设备的多个物理页面的对应物理页面的映射，其中所述间接表保持跟踪所述存储器设备中的所述一个或多个 地线。
-
公开(公告)号：US20150162528A1
公开(公告)日：2015-06-11
申请号：US14626945
申请日：2015-02-20
IPC分类号： H01L45/00
CPC分类号： H01L45/126 , H01L45/04 , H01L45/1226 , H01L45/144
摘要： A phase change memory (PCM) cell that includes a first electrode contacting a first layer of material having a first chemical composition. The PCM cell also includes a second layer of material having a second chemical composition and a second electrode contacting the first layer of material or the second layer of material. The PCM cell is configured for receiving at least one electrical current pulse flowing from the first electrode to the second electrode to locally heat a region of the first layer and the second layer to cause at least one of inter-diffusion and liquid mixing of the first layer of material and the second layer of material, resulting in a self-aligned region of phase change material having a chemical composition that is a mixture of the first chemical composition and the second chemical composition.
摘要翻译： 一种相变存储器（PCM）单元，其包括接触具有第一化学成分的第一材料层的第一电极。 PCM单元还包括具有第二化学成分的第二层材料和与第一材料层或第二材料层接触的第二电极。 PCM单元被配置用于接收从第一电极流向第二电极的至少一个电流脉冲，以局部加热第一层和第二层的区域，以引起第一和第二层之间的至少一个相互扩散和液体混合 材料层和第二层材料，导致相变材料的自对准区域具有作为第一化学组成和第二化学组合物的混合物的化学组成的自对准区域。
-
公开(公告)号：US08995217B2
公开(公告)日：2015-03-31
申请号：US13783729
申请日：2013-03-04
发明人： Michele M. Franceschini , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano
CPC分类号： G11C29/42 , G11C17/18 , G11C29/4401 , G11C29/789 , G11C2029/0409 , G11C2029/4402
摘要： A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.
摘要翻译： 描述了一种用于管理电子系统中的存储器的方法和装置。 该方法包括确定可由冗余元件修复的存储器阵列的元件中的故障。 该方法还可以包括使用锁存器来识别冗余元件。 该方法还可以包括在事件时，使用随后选择冗余元素的eFuse中的锁存器中的值。
-
公开(公告)号：US08880834B2
公开(公告)日：2014-11-04
申请号：US14160590
申请日：2014-01-22
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F11/1658 , G06F11/1666 , G06F12/02
摘要： Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
摘要翻译： 持续数据存储由计算机程序产品提供，该计算机程序产品包括被配置用于接收包括写入数据的低延迟存储命令的计算机程序代码。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。
-
公开(公告)号：US20140195765A1
公开(公告)日：2014-07-10
申请号：US13738035
申请日：2013-01-10
IPC分类号： G06F12/06
CPC分类号： G06F12/10 , G06F11/1004 , G06F11/1008 , G06F12/1081 , G06F12/145 , G06F2212/206
摘要： A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于实现用户模式外部设备到计算机系统中的存储器通道的附接。 使用设备寄存器和设备缓冲区的存储器映射将处理器地址空间附加到存储器通道上的用户模式外部设备。 设备上的存储容量在地址空间中被双重映射，创建单独的控制和数据地址空间，以允许用户模式进程控制设备，从而无需进行软件系统调用。 处理器内存管理单元（MMU）协调访问设备寄存器和缓冲区的多个用户进程，提供每个接口的地址空间保护，将设备保护从系统软件转移到处理器MMU。
-
公开(公告)号：US20140185397A1
公开(公告)日：2014-07-03
申请号：US13732954
申请日：2013-01-02
发明人： Michele M. Franceschini , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano
IPC分类号： G11C29/04
CPC分类号： G11C29/42 , G11C17/18 , G11C29/4401 , G11C29/789 , G11C2029/0409 , G11C2029/4402
摘要： A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.
-
公开(公告)号：US11537290B2
公开(公告)日：2022-12-27
申请号：US14220471
申请日：2014-03-20
摘要： There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.
-
公开(公告)号：US11157833B2
公开(公告)日：2021-10-26
申请号：US15921084
申请日：2018-03-14
摘要： An example operation may include one or more of partitioning a data set from a data provider into a training data set and a test data set, exposing the training data set to a learning service provider while preventing the learning service provider from being able to access the test data set, wherein the preventing comprises encrypting the test data set and storing the encrypted test data set in an immutable ledger, receiving a learning model that is generated by the learning service provider based on the exposed training data set, executing the received learning model using the test data set as input to verify whether the learning model satisfies a predefined performance threshold, and in response to verifying the learning model satisfies the predefined performance threshold, outputting information about the verification to a computing node.
-
公开(公告)号：US10963794B2
公开(公告)日：2021-03-30
申请号：US16530206
申请日：2019-08-02
发明人： Emrah Acar , Rajesh R. Bordawekar , Michele M. Franceschini , Luis A. Lastras-Montano , Ruchir Puri , Haifeng Qian , Livio B. Soares
IPC分类号： G06N5/00 , G06N5/02 , G06F16/36 , G06F16/245
摘要： Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.
-
-
-
-
-
-
-
-
-
搜索结果
96 条记录 (耗时 0.022 秒)
