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公开(公告)号：US20150309941A1
公开(公告)日：2015-10-29
申请号：US14264463
申请日：2014-04-29
IPC分类号： G06F12/10
CPC分类号： G11C11/418 , G06F12/10
摘要： An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines.
摘要翻译： 本发明的一个方面是用于在存储器件中提供PreSET区域的方法，其中PreSET区域包括已经被PreSET存储器件的一行或多行; 通过写入PreSET区域而不是写入到存储器件的位置线来对存储器件的一个或多个不合适的行执行写入操作; 以及在所述间接表中存储所述存储器设备的相应多个逻辑页面中的每一个到所述存储器设备的多个物理页面的对应物理页面的映射，其中所述间接表保持跟踪所述存储器设备中的所述一个或多个 地线。
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公开(公告)号：US10068639B2
公开(公告)日：2018-09-04
申请号：US14264463
申请日：2014-04-29
IPC分类号： G11C11/418
摘要： An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines.
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公开(公告)号：US20160314072A1
公开(公告)日：2016-10-27
申请号：US15200572
申请日：2016-07-01
IPC分类号： G06F12/0864 , G06F12/0895 , G06F12/128 , G06F12/0873
CPC分类号： G06F12/0864 , G06F12/0873 , G06F12/0895 , G06F12/121 , G06F12/128 , G06F2212/1016 , G06F2212/1056 , G06F2212/281 , G06F2212/305 , G06F2212/313 , G06F2212/6032 , G06F2212/6082
摘要： A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.
摘要翻译： 称为概率集关联缓存（PAC）的计算机高速缓冲存储器组织具有直接映射高速缓存的硬件复杂性和延迟，但在一小部分时间内用作集合关联高速缓存，从而比直接映射高速缓存命中率更好。 该组织被认为是（1 + P）组合关联高速缓存，其中所选择的参数“覆盖概率P”决定了平均关联性，例如，对于P = 0.1，其实际上它像1.1路组合关联高速缓存一样运行。
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公开(公告)号：US09037930B2
公开(公告)日：2015-05-19
申请号：US13769976
申请日：2013-02-19
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G11C29/00 , G11C11/406 , G11C11/4076 , G11C29/02 , G11C29/44 , G11C11/40
CPC分类号： G11C29/70 , G11C11/40 , G11C11/406 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/44 , G11C2029/4402 , G11C2211/4061 , G11C2211/4062
摘要： This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
摘要翻译： 该公开内容包括一种用于防止由于弱电池而导致的DRAM（动态随机存取存储器）中的错误的方法，所述弱电池包括确定DRAM行中的弱电池的位置，接收写入DRAM的数据，以及将数据编码为位 向量写入记忆。 对于每个弱小区位置，来自位向量的相应位等于弱小区的可靠逻辑状态，比特向量比数据长。
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公开(公告)号：US09087612B2
公开(公告)日：2015-07-21
申请号：US13780205
申请日：2013-02-28
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Moinuddin K. Qureshi
CPC分类号： G11C29/42 , G06F11/10 , G06F11/1048 , G11C7/04 , G11C7/1006 , G11C29/4401 , G11C29/50016 , G11C2029/0409 , G11C2029/0411 , G11C2029/4402
摘要： Errors on a dynamic random access memory (“DRAM”) having an error correcting decoder (“ECC”) can be detected by the ECC when reading a row of the DRAM. The ECC includes error correcting code logic. If errors are detected that cannot be corrected by the ECC logic, test control logic determines weak cell information for the row, evaluates the errors using the weak cell information, and may correct the errors. The weak cell information may include weak cell locations and failure values.
摘要翻译： 当读取一行DRAM时，ECC可以检测出具有纠错解码器（“ECC”）的动态随机存取存储器（“DRAM”）的错误。 ECC包括纠错码逻辑。 如果检测到不能被ECC逻辑校正的错误，则测试控制逻辑确定行的弱小区信息，使用弱小区信息来评估错误，并且可以校正错误。 弱小区信息可能包括弱小区位置和故障值。
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公开(公告)号：US08887014B2
公开(公告)日：2014-11-11
申请号：US13710551
申请日：2012-12-11
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C29/70 , G11C11/40 , G11C11/406 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/44 , G11C2029/4402 , G11C2211/4061 , G11C2211/4062
摘要： This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
摘要翻译： 该公开内容包括一种用于防止由于弱电池而导致的DRAM（动态随机存取存储器）中的错误的方法，所述弱电池包括确定DRAM行中的弱电池的位置，接收写入DRAM的数据，以及将数据编码为位 向量写入记忆。 对于每个弱小区位置，来自位向量的相应位等于弱小区的可靠逻辑状态，比特向量比数据长。
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公开(公告)号：US20140164871A1
公开(公告)日：2014-06-12
申请号：US13710561
申请日：2012-12-11
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G11C29/42
CPC分类号： G11C29/42 , G06F11/10 , G06F11/1048 , G11C7/04 , G11C7/1006 , G11C29/4401 , G11C29/50016 , G11C2029/0409 , G11C2029/0411 , G11C2029/4402
摘要： This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.
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公开(公告)号：US20140164820A1
公开(公告)日：2014-06-12
申请号：US13710551
申请日：2012-12-11
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G11C29/00
CPC分类号： G11C29/70 , G11C11/40 , G11C11/406 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/44 , G11C2029/4402 , G11C2211/4061 , G11C2211/4062
摘要： This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
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公开(公告)号：US10019370B2
公开(公告)日：2018-07-10
申请号：US15200572
申请日：2016-07-01
IPC分类号： G06F12/02 , G06F12/0864 , G06F12/121 , G06F12/0873 , G06F12/0895 , G06F12/128
CPC分类号： G06F12/0864 , G06F12/0873 , G06F12/0895 , G06F12/121 , G06F12/128 , G06F2212/1016 , G06F2212/1056 , G06F2212/281 , G06F2212/305 , G06F2212/313 , G06F2212/6032 , G06F2212/6082
摘要： A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.
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公开(公告)号：US20140164692A1
公开(公告)日：2014-06-12
申请号：US13769976
申请日：2013-02-19
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G11C11/406
CPC分类号： G11C29/70 , G11C11/40 , G11C11/406 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/44 , G11C2029/4402 , G11C2211/4061 , G11C2211/4062
摘要： This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
摘要翻译： 该公开内容包括一种用于防止由于弱电池而导致的DRAM（动态随机存取存储器）中的错误的方法，所述弱电池包括确定DRAM行中的弱电池的位置，接收写入DRAM的数据，以及将数据编码为位 向量写入记忆。 对于每个弱小区位置，来自位向量的相应位等于弱小区的可靠逻辑状态，比特向量比数据长。
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