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公开(公告)号：US20140089734A1
公开(公告)日：2014-03-27
申请号：US13628104
申请日：2012-09-27
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/14
CPC分类号： G06F11/2023 , G06F11/0715 , G06F11/0724 , G06F11/076 , G06F11/1658 , G06F11/2025 , G06F11/203 , G06F11/2043
摘要： Embodiments relate to thread sparing between cores in a processor. An aspect includes determining that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold, and sending a request to transfer the first thread. Another aspect includes, selecting a second core from a plurality of cores to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread. Another aspect includes transferring a last good architected state of the first thread from the first core to the second core. Another aspect includes loading the last good architected state of the first thread by the idle thread on the second core. Yet another aspect includes resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread.
摘要翻译： 实施例涉及处理器中的核之间的线程间隔。 一方面包括确定由第一核心上的第一线程进行的恢复尝试的次数已经超过恢复尝试阈值，并且发送传送第一线程的请求。 另一方面包括：从多个芯选择第二芯以从第一芯接收第一线，其中基于具有空闲线的第二芯选择第二芯。 另一方面包括将第一线程的最后一个良好架构状态从第一核心传输到第二核心。 另一方面包括通过第二核心上的空闲线程加载第一线程的最后良好的架构状态。 又一方面包括从空闲线程的第一线程的最后良好架构状态恢复第二核心上的第一线程的执行。
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公开(公告)号：US20140089732A1
公开(公告)日：2014-03-27
申请号：US13783797
申请日：2013-03-04
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/20
CPC分类号： G06F11/2023 , G06F11/0715 , G06F11/0724 , G06F11/076 , G06F11/1658 , G06F11/2025 , G06F11/203 , G06F11/2043
摘要： Embodiments relate to thread sparing between cores in a processor. An aspect includes determining that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold, and sending a request to transfer the first thread. Another aspect includes, selecting a second core from a plurality of cores to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread. Another aspect includes transferring a last good architected state of the first thread from the first core to the second core. Another aspect includes loading the last good architected state of the first thread by the idle thread on the second core. Yet another aspect includes resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread.
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公开(公告)号：US20140082626A1
公开(公告)日：2014-03-20
申请号：US13783334
申请日：2013-03-03
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/38 , G06F9/45533 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F9/5016 , G06F9/5077 , G06F2009/45591 , G06F2209/483 , G06F2209/5021 , G06F2209/504 , G06F2209/507 , G06F2209/508 , Y02B70/30 , Y02D10/22
摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).
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公开(公告)号：US20130198497A1
公开(公告)日：2013-08-01
申请号：US13678217
申请日：2012-11-15
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467 , G06F9/528
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.
摘要翻译： 提供了主要分支指令，其使得能够执行计算机程序从一段代码分支到另一段代码。 这些指令还在代码的另一部分创建一个新的处理流，从而能够执行要与分支进行分割的代码段并行执行的其他代码段。 在一个示例中，另一个处理流开始处理另一个处理流的指令的事务。
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75.发明授权公开(公告)号：US11587600B2
公开(公告)日：2023-02-21
申请号：US16397154
申请日：2019-04-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Warren E. Maule , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
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公开(公告)号：US10740031B2
公开(公告)日：2020-08-11
申请号：US16140780
申请日：2018-09-25
摘要： An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.
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77.发明申请公开(公告)号：US20200042205A1
公开(公告)日：2020-02-06
申请号：US16598103
申请日：2019-10-10
发明人： Steven R. Carlough , Susan M. Eickhoff , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
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78.发明授权公开(公告)号：US10534555B2
公开(公告)日：2020-01-14
申请号：US15825909
申请日：2017-11-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
IPC分类号： G06F3/06
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
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公开(公告)号：US10530396B2
公开(公告)日：2020-01-07
申请号：US15817387
申请日：2017-11-20
摘要： Aspects of the invention include monitoring frames of bits received at a receiver for transmission errors. At least one of the received frames of bits includes cyclic redundancy code (CRC) bits for a first type of CRC check. It is determined whether a change in transmission errors has occurred in the received frames by performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames. A change from the first type of CRC check to a second type of CRC check is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred. The change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver.
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公开(公告)号：US10445066B2
公开(公告)日：2019-10-15
申请号：US15432462
申请日：2017-02-14
摘要： Embodiments are directed to a computer implemented method for executing machine instructions in a central processing unit. The method includes obtaining, by a processor system, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture. The method further includes executing the machine instruction, wherein the executing includes loading a multiplicand into a multiplicand register, and loading a multiplier into a multiplier register. The executing further generates an intermediate product having least significant bits by multiplying the multiplicand and the multiplier. The executing further includes generating a rounded product by performing a probability analysis on the least significant bits of the intermediate product, and initiating a rounding operation on the intermediate product to produce the rounded product based at least in part on the probability analysis.
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