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    Command processing for graphics tile-based rendering
    78.
    发明授权
    Command processing for graphics tile-based rendering 有权

    公开(公告)号：US10068307B2

    公开(公告)日：2018-09-04

    申请号：US15159897

    申请日：2016-05-20

    Applicant: Intel Corporation

    Inventor： Balaji Vembu ,  Peter L. Doyle ,  Michael Apodaca ,  Hema C. Nalluri ,  Jeffery S. Boles

    IPC: G06T15/40 ,  G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06T1/60

    Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.

    SUPPORTING MULTI-LEVEL NESTING OF COMMAND BUFFERS IN GRAPHICS COMMAND STREAMS AT COMPUTING DEVICES
    79.
    发明申请
    SUPPORTING MULTI-LEVEL NESTING OF COMMAND BUFFERS IN GRAPHICS COMMAND STREAMS AT COMPUTING DEVICES 有权
    在计算机设备的图形命令流中支持多层次的命令缓存

    公开(公告)号：US20160307290A1

    公开(公告)日：2016-10-20

    申请号：US14686476

    申请日：2015-04-14

    Applicant: INTEL CORPORATION

    Inventor： HEMA CHAND NALLURI ,  Balaji Vembu ,  Jeffery S. Boles

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06F12/00 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/455 ,  G06T1/60

    Abstract: A mechanism is described for facilitating multi-level nesting of batch buffers at computing devices. A method of embodiments, as described herein, includes facilitating a hardware extension to accommodate a plurality of batch buffers to engage in a multi-level nesting, where the plurality of batch buffers are associated with a graphics processor of a computing device. The method may further include facilitating the multi-level nesting of the plurality of batch buffers, where the multi-level nesting is spread over a plurality of levels associated with the plurality of batch buffers, where the plurality of levels include more than two levels of nesting associated with more than two batch buffers of the plurality of batch buffers.

    Abstract translation: 描述了一种机制，用于促进计算设备上批量缓冲区的多级嵌套。 如本文所述的实施例的方法包括促进硬件扩展以容纳多个批次缓冲器以参与多级嵌套，其中多个批处理缓冲器与计算设备的图形处理器相关联。 该方法还可以包括促进多级批量缓冲器的多级嵌套，其中多级嵌套分布在与多个批处理缓冲器相关联的多个级别上，其中多个级别包括多于两级的 与多个批次缓冲器中的两个以上批处理缓冲器相关联的嵌套。

    Priority based context preemption
    80.
    发明授权
    Priority based context preemption 有权
    基于优先级的上下文抢占

    公开(公告)号：US09396032B2

    公开(公告)日：2016-07-19

    申请号：US14227692

    申请日：2014-03-27

    Applicant: Intel Corporation

    Inventor： Hema C. Nalluri ,  Aditya Navale ,  Peter L. Doyle ,  Murali Ramadoss ,  Balaji Vembu ,  Jeffery S. Boles

    IPC: G06F9/46 ,  G06F9/50 ,  G06T1/20

    CPC classification number: G06F9/5038 ,  G06T1/20

    Abstract: Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.

    Abstract translation: 方法和设备可以优先处理通过单独的高优先级和低优先级上下文提交端口提交给处理单元的高优先级和低优先权上下文。 根据一个实施例，向低优先级端口提交上下文导致正在进行的上下文被抢占，而向高优先级端口提交上下文导致正在进行的上下文被暂停。

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