公开(公告)号：US20200303373A1

公开(公告)日：2020-09-24

申请号：US16649386

申请日：2017-12-28

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/205 ,  H01L29/786 ,  H01L29/423

摘要： Techniques are disclosed for using compositionally different contact materials for p-type and n-type source/drain regions on a common substrate. The different contact materials may be within a common source/drain contact trench, or in type-dedicated trenches. A given contact trench may span one or more fins and include one or more source/drain regions on which a corresponding contact structure is to be made. In an embodiment, an isolation structure between p-type and n-type fins is selective to the trench etch and therefore remains intact within the trench after the target source/drain regions have been exposed. In such cases, the isolation structure physically separates n-type source/drain regions from p-type source/drain regions. The contact structures on the different type source/drain regions may be shorted proximate the top of the isolation structure. Numerous material systems can be used for the channel and source/drain regions, including germanium, group III-V materials, and 2-D materials.

公开(公告)号：US20200279910A1

公开(公告)日：2020-09-03

申请号：US16649287

申请日：2017-12-15

申请人： INTEL CORPORATION

发明人： Dipanjan Basu ,  Cory E. Weber ,  Justin R. Weber ,  Sean T. Ma ,  Harold W. Kennel ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/205 ,  H01L29/161 ,  H01L29/775

摘要： Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

公开(公告)号：US10755984B2

公开(公告)日：2020-08-25

申请号：US15576396

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Ying Pang ,  Nabil G. Mistkawi ,  Anand S. Murthy ,  Tahir Ghani ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66

摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

公开(公告)号：US20200258738A1

公开(公告)日：2020-08-13

申请号：US16074350

申请日：2016-04-01

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy

IPC分类号： H01L21/02 ,  H01L21/84 ,  H01L29/78

摘要： The present disclosure provides systems and methods for a layered substrate. A layered substrate may include a core comprising graphite. The layered substrate may also include a coating layer comprising a coating material that surrounds the core, wherein the coating material has a melting point that is greater than a melting point of silicon.

公开(公告)号：US20200219986A1

公开(公告)日：2020-07-09

申请号：US16242670

申请日：2019-01-08

申请人： Intel Corporation

发明人： Han Wui Then ,  Marko Radosavljevic ,  Glenn A. Glass ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L21/265

摘要： Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

公开(公告)号：US20200152750A1

公开(公告)日：2020-05-14

申请号：US16487077

申请日：2017-03-28

申请人： Intel Corporation

发明人： Patrick Morrow ,  Glenn A. Glass ,  Anand S. Murthy ,  Rishabh Mehandru

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

摘要： Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

公开(公告)号：US10559683B2

公开(公告)日：2020-02-11

申请号：US15504171

申请日：2014-09-19

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/201 ,  H01L29/423

摘要： Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

公开(公告)号：US10553680B2

公开(公告)日：2020-02-04

申请号：US16402739

申请日：2019-05-03

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L21/3215 ,  H01L27/092 ,  H01L29/417 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/36 ,  H01L21/02 ,  H01L29/167 ,  H01L29/49 ,  H01L29/165 ,  H01L29/423

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US10461193B2

公开(公告)日：2019-10-29

申请号：US15575322

申请日：2015-05-27

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Gilbert Dewey ,  Anand S. Murthy ,  Glenn A. Glass ,  Willy Rachmady ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz

IPC分类号： H01L29/00 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

摘要： Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.

公开(公告)号：US20190273133A1

公开(公告)日：2019-09-05

申请号：US16347110

申请日：2016-12-14

申请人： Intel Corporation

发明人： Ashish Agrawal ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Glenn A. Glass ,  Van H. Le ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Willy Rachmady

IPC分类号： H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/45 ,  H01L29/417 ,  H01L29/10

摘要： Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.