公开(公告)号：US20110206151A1

公开(公告)日：2011-08-25

申请号：US12711128

申请日：2010-02-23

申请人： Michael L. McCloud ,  Matthias Brehler ,  Ju Won Park ,  Jong Hyeon Park ,  Je Woo Kim ,  Inyup Kang ,  Brian C. Banister

发明人： Michael L. McCloud ,  Matthias Brehler ,  Ju Won Park ,  Jong Hyeon Park ,  Je Woo Kim ,  Inyup Kang ,  Brian C. Banister

IPC分类号： H04L1/02 ,  H04L27/06

CPC分类号： H04L25/03229 ,  H04B7/0413 ,  H04L25/03242 ,  H04L25/03318 ,  H04L2025/0342 ,  H04L2025/03426

摘要： Providing for reduced complexity or improved accuracy in de-mapping received wireless data streams for multi-channel wireless communication is described herein. By way of example, a low-complexity likelihood algorithm can be employed to de-map data bits from the wireless data streams. In one particular example, the likelihood algorithm can approximate a received bit with a subset of received wireless symbols correlated the bit, reducing algorithm complexity. In other examples, a limited set of received wireless symbols can be employed for the subset, further reducing algorithm complexity. According to at least one other example, logarithmic terms of the algorithm can be approximated with non-logarithmic functions, such as a look-up table, series expansion, polynomial approximation, or the like. These approximations can enhance symbol de-mapping accuracy while maintaining or improving processing overhead for a wireless receiver.

摘要翻译： 本文描述了为了解复用用于多信道无线通信的接收的无线数据流而提供降低的复杂度或提高的精度。 作为示例，可以采用低复杂度似然算法来从无线数据流解映射数据比特。 在一个特定示例中，似然算法可以用接收到的无线符号的子集近似接收到的比特，从而降低算法的复杂度。 在其他示例中，可以对该子集采用有限的一组接收到的无线符号，进一步降低了算法的复杂度。 根据至少另一个示例，算法的对数项可以用非对数函数来近似，例如查找表，串联展开，多项式近似等。 这些近似可以增强符号解映射精度，同时保持或改善无线接收机的处理开销。

公开(公告)号：US07949351B2

公开(公告)日：2011-05-24

申请号：US12277104

申请日：2008-11-24

申请人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang

发明人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang

IPC分类号： H04Q7/20

CPC分类号： G01S5/0036 ,  G01S19/235 ,  G01S19/254 ,  G01S19/258 ,  G01S19/30

摘要： The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location on a subscriber unit in a terrestrial wireless telephone system using a set of satellites each transmitting a signal, the terrestrial wireless telephone system having base stations, including the steps of transmitting an aiding message from the base station to the subscriber unit, said aiding message containing information regarding a data boundary for each signal from the set of satellites, applying correlation codes to each signal yielding corresponding correlation data and accumulating said correlation data over an first interval preceding a corresponding data boundary yielding a first accumulation result, and a second interval following said corresponding data boundary yielding a second accumulation result.

摘要翻译： 本发明是一种用于在无线通信系统中执行位置定位的新颖且改进的方法和装置。 本发明的一个实施例包括一种用于在陆地无线电话系统中的用户单元上执行位置定位的方法，该方法使用一组发射信号的卫星，具有基站的地面无线电话系统包括以下步骤：从 基站到用户单元，所述辅助消息包含关于来自卫星组的每个信号的数据边界的信息，将相关代码应用于产生相应相关数据的每个信号，并在对应的数据边界之前的第一间隔上累加所述相关数据 产生第一累积结果，并且在所述对应数据边界之后的第二间隔产生第二累积结果。

公开(公告)号：US07656935B2

公开(公告)日：2010-02-02

申请号：US11621145

申请日：2007-01-09

申请人： Inyup Kang ,  Mark Roh ,  Brendon L. Johnson

发明人： Inyup Kang ,  Mark Roh ,  Brendon L. Johnson

IPC分类号： H04B1/707

CPC分类号： H04B1/70758 ,  H04B1/70757 ,  H04B1/7117

摘要： In general, the invention facilitates searching for energy peaks in spread spectrum wireless communication systems with greater precision. More particularly, various embodiments of the invention may involve reporting not only an energy peak and its associated offset, but also the energy levels corresponding to one or more offsets occurring before and after the offset at which the energy peak occurs. Interpolation or extrapolation techniques may be used to predict the actual location of an energy peak based on the apparent location of the peak and the energy levels observed at surrounding offsets.

摘要翻译： 通常，本发明有助于以更高的精度搜索扩频无线通信系统中的能量峰值。 更具体地，本发明的各种实施例可以包括不仅报告能量峰值及其相关联的偏移，还报告对应于发生能量峰值的偏移之前和之后发生的一个或多个偏移的能级。 可以使用插值或外插技术来基于峰值的表观位置和在周围偏移处观察到的能量水平来预测能量峰值的实际位置。

公开(公告)号：US20080112381A1

公开(公告)日：2008-05-15

申请号：US11560060

申请日：2006-11-15

申请人： Byonghyo Shim ,  Farrokh Abrishamkar ,  Inyup Kang

发明人： Byonghyo Shim ,  Farrokh Abrishamkar ,  Inyup Kang

IPC分类号： H04B7/216

CPC分类号： H04B1/71072 ,  H04B1/71055 ,  H04B1/71075 ,  H04B1/7115 ,  H04B2201/70702

摘要： Techniques for recovering a desired transmission in the presence of interfering transmissions are described. For iterative detection and cancellation, multiple groups of code channels are formed for a plurality of code channels for at least one sector. Processing is performed for the multiple groups of code channels in multiple iterations. For each iteration, data detection and signal cancellation are performed for the multiple groups of code channels in multiple stages, e.g., in a sequential order starting with the strongest group to the weakest group. Each stage of each iteration may perform data detection, signal reconstruction, and signal cancellation. Each stage of each iteration may also perform equalization, data detection, signal reconstruction, and signal cancellation.

摘要翻译： 描述了在存在干扰传输的情况下恢复所需传输的技术。 对于迭代检测和消除，针对至少一个扇区的多个代码信道形成多组代码信道组。 在多个迭代中针对多组代码信道执行处理。 对于每个迭代，对于多个阶段的多组代码信道执行数据检测和信号消除，例如以从最强组到最弱组的顺序顺序执行。 每个迭代的每个阶段都可以执行数据检测，信号重建和信号消除。 每个迭代的每个阶段也可以执行均衡，数据检测，信号重建和信号消除。

公开(公告)号：US07369815B2

公开(公告)日：2008-05-06

申请号：US10786585

申请日：2004-02-24

申请人： Inyup Kang ,  Karthikeyan Ethirajan

发明人： Inyup Kang ,  Karthikeyan Ethirajan

IPC分类号： H04B1/16 ,  H04M1/00

CPC分类号： H04W52/028 ,  Y02D70/122 ,  Y02D70/1242 ,  Y02D70/144

摘要： An integrated circuit for a modem processor includes processing units that are partitioned into “always-on” and “collapsible” power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing units in the power domain are not needed. A power control unit within an always-on power domain powers down the collapsible power domains after going into sleep and powers up these domains after waking up from sleep. Tasks for powering down the collapsible power domains may include (1) saving pertinent hardware registers for these power domains, (2) freezing output pins of the IC to minimally disturb external units, (3) clamping input pins of the collapsed power domains, (4) powering down a main oscillator and disabling the oscillator clock, and so on. Complementary tasks are performed for powering up the collapsed power domains.

摘要翻译： 用于调制解调器处理器的集成电路包括被划分为“永远在线”和“可折叠”电力域的处理单元。 永远在线的电源域始终打开。 如果不需要电源域中的处理单元，则可以关闭可折叠电源域。 永远在线的电源域内的电源控制单元在睡眠后唤醒可折叠的电源域，并在从睡眠中唤醒之后启动这些域。 关闭可折叠电源域的任务可能包括（1）保存这些电源域的相关硬件寄存器，（2）冻结IC的输出引脚以最小限度地干扰外部单元，（3）钳位崩溃的电源域的输入引脚（ 4）关闭主振荡器并禁用振荡器时钟，等等。 执行补充任务以加电折叠的电源域。

公开(公告)号：US07076225B2

公开(公告)日：2006-07-11

申请号：US10034734

申请日：2001-12-21

申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

IPC分类号： H04B7/00

CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

公开(公告)号：US20050064829A1

公开(公告)日：2005-03-24

申请号：US10786585

申请日：2004-02-24

申请人： Inyup Kang ,  Karthikeyan Ethirajan

发明人： Inyup Kang ,  Karthikeyan Ethirajan

IPC分类号： H04W52/02 ,  H04B1/16 ,  H04Q7/20

CPC分类号： H04W52/028 ,  Y02D70/122 ,  Y02D70/1242 ,  Y02D70/144

摘要： An integrated circuit for a modem processor includes processing units that are partitioned into “always-on” and “collapsible” power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing units in the power domain are not needed. A power control unit within an always-on power domain powers down the collapsible power domains after going into sleep and powers up these domains after waking up from sleep. Tasks for powering down the collapsible power domains may include (1) saving pertinent hardware registers for these power domains, (2) freezing output pins of the IC to minimally disturb external units, (3) clamping input pins of the collapsed power domains, (4) powering down a main oscillator and disabling the oscillator clock, and so on. Complementary tasks are performed for powering up the collapsed power domains.

摘要翻译： 用于调制解调器处理器的集成电路包括被划分为“永远在线”和“可折叠”电力域的处理单元。 永远在线的电源域始终打开。 如果不需要电源域中的处理单元，则可以关闭可折叠电源域。 永远在线的电源域内的电源控制单元在睡眠后唤醒可折叠的电源域，并在从睡眠中唤醒之后启动这些域。 关闭可折叠电源域的任务可能包括（1）保存这些电源域的相关硬件寄存器，（2）冻结IC的输出引脚以最小限度地干扰外部单元，（3）钳位崩溃的电源域的输入引脚（ 4）关闭主振荡器并禁用振荡器时钟，等等。 执行补充任务以加电折叠的电源域。

公开(公告)号：US06735240B1

公开(公告)日：2004-05-11

申请号：US09718275

申请日：2000-11-21

申请人： Inyup Kang

发明人： Inyup Kang

IPC分类号： H04B169

CPC分类号： H04B1/7117 ,  H04B1/712 ,  H04B2201/70703 ,  H04B2201/70707

摘要： A deskew buffer 410 arrangement in a CDMA receiver allows for accurate combining of symbols from a plurality of demodulator fingers, 402 and 404, without any symbol losses when the data rate is changed. A single deskew buffer 410 is coupled to a plurality of demodulator fingers, each of which demodulate an assigned multipath. The symbols are written into the deskew buffer 410 according to a PN count value modified by a predetermined bit pattern. The demodulator finger is able to demodulate a plurality of data rates corresponding to a plurality of Walsh lengths. Each data rate is assigned a corresponding deskew index. The PN count value represents an address within the deskew buffer 410. The lower bits of the PN count, where the number of bits corresponds to the deskew index, are truncated and replaced with the predetermined bit pattern. In one embodiment the predetermined bit pattern is all ones.

摘要翻译： CDMA接收机中的去歪斜缓冲器410配置允许来自多个解调器指状物402和404的符号的精确组合，而在数据速率改变时没有任何符号损失。 单个去歪斜缓冲器410耦合到多个解调器指状物，每个解调器指针解调所分配的多路径。 根据由预定位模式修改的PN计数值，将符号写入偏移缓冲器410。 解调器手指能够解调对应于多个沃尔什长度的多个数据速率。 每个数据速率被分配相应的偏斜指数。 PN计数值表示该偏移校正缓冲器410内的一个地址。位数对应于该偏斜校正索引的PN计数的较低位被截断，并以预定位模式替换。 在一个实施例中，预定位模式是全部的。

公开(公告)号：US06661851B1

公开(公告)日：2003-12-09

申请号：US09693112

申请日：2000-10-20

申请人： Inyup Kang

发明人： Inyup Kang

IPC分类号： H04L2722

CPC分类号： H04L27/0014 ,  H04L27/28

摘要： A bi-directional vector rotator that can be used to provide outputs having phases that are rotated in clockwise and counter clockwise directions relative to that of the input signal. The bi-directional vector rotator includes a product term generator that receives a complex input and a complex carrier signal and generates product terms. Combiners then selectively combine the product terms to generate the outputs. By sharing the same product term generator for both clockwise and counter clockwise phase rotations, the bi-directional vector rotator can be implemented using less circuitry than that for a conventional design employing two uni-directional vector rotators. Moreover, only one complex carrier signal is needed by the bi-directional vector rotator instead of two for the conventional design. Further simplification in the design of the bi-directional vector rotator can be achieved by selecting the proper sampling rate for the complex input. The bi-directional vector rotator can be advantageously used in a receiver device, and is especially efficient in demodulating a multi-carrier signal having multiple (e.g., three) modulated signals.

摘要翻译： 双向向量旋转器，可用于提供具有相对于输入信号顺时针和逆时针方向旋转的相位的输出。 双向向量旋转器包括产生项发生器，其接收复数输入和复数载波信号并产生乘积项。 然后，组合器选择性地组合产品术语以产生输出。 通过共享相同的产品术语发生器用于顺时针和逆时针相位旋转，双向向量旋转器可以使用比使用两个单向矢量旋转器的常规设计的电路更少的电路来实现。 此外，双向向量旋转器仅需要一个复合载波信号，而不是常规设计的两个。 双向矢量旋转器设计的进一步简化可以通过选择合成输入的适当采样率来实现。 双向向量旋转器可以有利地用在接收机设备中，并且在解调具有多个（例如，三个）调制信号的多载波信号方面特别有效。

公开(公告)号：US06615341B2

公开(公告)日：2003-09-02

申请号：US09876189

申请日：2001-06-05

申请人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

发明人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.