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公开(公告)号：US20110225402A1
公开(公告)日：2011-09-15
申请号：US13064108
申请日：2011-03-07
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30101 , G06F9/30189
摘要： Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.
摘要翻译： 处理电路4具有用于处理异常事件的多个异常状态EL0-EL3，异常状态包括基本电平异常状态EL0和至少一个进一步的电平异常状态EL1-EL3。 每个异常状态具有指示相应堆栈数据存储器35的存储器内的位置的相应堆栈指针。当处理电路处于基本电平异常状态EL0时，堆栈指针选择电路40选择基本电平堆栈指针作为当前堆栈 指示当前堆栈数据存储供处理电路4使用。当处理电路4是另外的异常状态时，堆栈指针选择电路40选择对应于当前进一步的基本级堆栈指针或进一步的级堆栈指针 级异常状态作为当前堆栈指针。
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公开(公告)号：US20110225397A1
公开(公告)日：2011-09-15
申请号：US12929865
申请日：2011-02-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30112 , G06F9/30123 , G06F9/30138 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/384 , G06F9/3863
摘要： A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.
摘要翻译： 提供处理器4，其支持指定32位架构寄存器的第一指令集和指定64位架构寄存器的第二指令集。 这些指令集中的每一个都带有自己的一组架构寄存器供使用。 呈现给第一指令集的第一组寄存器具有与呈现给该第二指令集的第二组寄存器的一对一映射。 在硬件中提供的寄存器是64位寄存器。 在一些实施例中，当执行第一指令集的程序指令时，只有这些64位寄存器的最低有效部分被访问和操作，其中最重要的寄存器部分保持不变。 在第一指令集的指令内的寄存器指定字段与当前异常模式一起被解码以确定要使用的架构寄存器，而第二指令集使用寄存器指定字段而不依赖于异常模式来确定要使用哪个架构寄存器。
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73.发明申请公开(公告)号：US20110213935A1
公开(公告)日：2011-09-01
申请号：US12659235
申请日：2010-03-01
CPC分类号： G06F1/3203 , G06F1/3293 , G06F9/5094 , Y02D10/122 , Y02D10/22
摘要： A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. The switch controller is arranged, during the handover operation, to cause the source processing circuitry to make its current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory shared between the first and second processing circuitry at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. Further, the source processing circuitry and second processing circuitry implement an accelerated mechanism to make the current architectural state available to the destination processing circuitry without routing of the current architectural state via the shared memory. Since the accelerated mechanism is quick and energy efficient, it increases the number of situations it which it is energy efficient to make the switch from one processing circuitry to the other.
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74.发明申请Storing secure mode page table data in secure and non-secure regions of memory 有权将安全模式页表数据存储在内存的安全和非安全区域公开(公告)号：US20110208935A1
公开(公告)日：2011-08-25
申请号：US12929766
申请日：2011-02-14
IPC分类号： G06F12/14
CPC分类号： G06F12/1009 , G06F12/145
摘要： Apparatus for data processing 2 is provided with processing circuitry 8 which operates in one or more secure modes 40 and one or more non-secure modes 42. When operating in a non-secure mode, one or more regions of the memory are inaccessible. A memory management unit 24 is responsive to page table data to manage accesses to the memory which includes a secure memory 22 and a non-secure memory 6. Secure mode page table data 36, 38 is used when operating in one of the secure modes. A page table entry within the hierarchy of page tables of the secure mode page table data includes a table security field 68, 72 indicating whether or not a further page table pointed to by that page table entry is stored within the secure memory 22 or the non-secure memory 6. If any of the page tables associated with a memory access are stored within the non-secure memory 6, then the memory access is marked with a table attribute bit NST indicating that the memory access should be treated as non-secure.
摘要翻译： 用于数据处理2的装置设置有处理电路8，其在一个或多个安全模式40和一个或多个非安全模式42中操作。当以非安全模式操作时，存储器的一个或多个区域是不可访问的。 存储器管理单元24响应于页表数据来管理对包括安全存储器22和非安全存储器6的存储器的访问。当以安全模式之一操作时，使用安全模式页表数据36,38。 安全模式页表数据的页表层次结构中的页表项包括表安全字段68,72，指示该页表项所指向的另一页表是否存储在安全存储器22内， 如果与存储器访问相关联的任何页表存储在非安全存储器6内，则存储器访问用表属性位NST标记，表示存储器访问应被视为不安全的 。
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75.发明申请Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag 有权限制根据硬件模式和安全标志读取的指令的存储区公开(公告)号：US20110202739A1
公开(公告)日：2011-08-18
申请号：US12656786
申请日：2010-02-16
CPC分类号： G06F12/1491 , G06F21/52 , G06F21/74 , G06F21/79 , G06F2221/2105
摘要： An apparatus for processing data 2 includes a processor 8, a memory 6 and memory control circuitry 12. The processor 8 operates in a plurality of hardware modes including a privileged mode and a user mode. When operating in the privileged mode, the processor 8 is blocked by the memory control circuitry 12 from fetching instructions from memory address regions 34, 38, 42 within the memory 6 which are writeable within the user mode if a security flag within register 46 is set to indicate that this blocking mechanism is active.
摘要翻译： 处理数据2的装置包括处理器8，存储器6和存储器控制电路12.处理器8以包括特权模式和用户模式的多种硬件模式操作。 当在特权模式下操作时，处理器8被存储器控制电路12阻止从存储器6中的存储器地址区域34,38,42中获取指令，这些指令可在用户模式内写入，如果寄存器46内的安全标志被设置 以指示该阻塞机制是活动的。
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公开(公告)号：US07966466B2
公开(公告)日：2011-06-21
申请号：US12068449
申请日：2008-02-06
IPC分类号： G06F12/00
CPC分类号： G06F12/1483 , G06F9/30076
摘要： Access to memory address space is controlled by memory access control circuitry using access control data. The ability to change the access control data is controlled by domain control circuitry. Whether or not an instruction stored within a particular domain, being a set of memory addresses, is able to modify the access control data is dependent upon the domain concerned. Thus, the ability to change access control data can be restricted to instructions stored within particular defined locations within the memory address space thereby enhancing security. This capability allows systems to be provided in which call forwarding to an operating system can be enforced via call forwarding code and where trusted regions of the memory address space can be established into which a secure operating system may write data with increased confidence that that data will only be accessible by trusted software executing under control of a non-secure operating system.
摘要翻译： 使用访问控制数据的存储器访问控制电路控制对存储器地址空间的访问。 更改访问控制数据的能力由域控制电路控制。 作为一组存储器地址的存储在特定域内的指令是否能够修改访问控制数据取决于所涉及的域。 因此，改变访问控制数据的能力可以被限制为存储在存储器地址空间内的特定定义位置内的指令，从而增强安全性。 该功能允许提供系统，其中可以通过呼叫转移代码来实施对操作系统的呼叫转移，并且可以建立存储器地址空间的可信区域，安全操作系统可以以更高的置信度写入数据，该数据将 只能通过在非安全操作系统的控制下执行的可信软件来访问。
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77.发明授权Data transfer between an external data source and a memory associated with a data processor 有权外部数据源与与数据处理器相关联的存储器之间的数据传输公开(公告)号：US07254667B2
公开(公告)日：2007-08-07
申请号：US10815982
申请日：2004-04-02
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 operable to perform further data processing operations in response to receipt of said processor clock signal CLK. The two portions of the core being operable to be independently enabled such that one portion may be active while the other is inactive.
摘要翻译： 数据处理器核心10，其包括存储器访问接口部分30，其可操作以在外部数据源与至少一个与所述数据处理器核心相关联的存储器之间执行数据传输操作;以及数据处理部分12，可操作以执行另外的数据处理操作 接收所述处理器时钟信号CLK。 核心的两个部分可操作以独立地启用，使得一个部分可以是活动的，而另一个部分是不活动的。
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公开(公告)号：US07047401B2
公开(公告)日：2006-05-16
申请号：US10461335
申请日：2003-06-16
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3861
摘要： A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to respective memory locations or to store data values from multiple memory locations to respective program registers. A memory management unit 8 within the system stores device or strongly ordered memory attribute values which control whether or not a multiple memory access instruction involving such a memory location may be early terminated when an interrupt is received during its operation. Early termination is permitted in those circumstances where the multiple memory access instruction may be safely restarted and rerun in its entirety, whereas early termination is not permitted and the operation completes before the interrupt is taken in those circumstances where the memory locations are subject to a guaranteed number of memory accesses as this appears within the controlling program instructions.
摘要翻译： 数据处理装置2支持用于将来自多个程序寄存器16的数据值加载到相应存储器位置的多个存储器访问程序指令LDM，STM或将多个存储器位置的数据值存储到各个程序寄存器。 系统内的存储器管理单元8存储设备或强有序的存储器属性值，其控制在其操作期间接收到中断时是否可能提前终止涉及这样的存储器位置的多存储器访问指令。 在多重内存访问指令可以安全地重新启动并全部重新运行的情况下，允许提前终止，而不允许提前终止，并且在内存位置受到保证的情况下中断之前，操作完成 存储器访问次数显示在控制程序指令内。
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公开(公告)号：US07024543B2
公开(公告)日：2006-04-04
申请号：US10242671
申请日：2002-09-13
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： The present invention provides an apparatus and method for synchronizing a first pipeline and a second pipeline of a processor arranged to execute a sequence of instructions. The processor is arranged to route an instruction in the sequence through either the first or the second pipeline dependent on predetermined criteria, each pipeline having a plurality of pipeline stages including a retirement stage. Counter logic is provided for maintaining a first counter relating to the first pipeline and a second counter relating to the second pipeline. For each instruction in the first pipeline a determination is made as to when that instruction reaches a point within the first pipeline where an exception status of that instruction is resolved, and the counter logic is arranged to increment the first counter responsive to such determination. The processor is arranged to generate an indication within the second pipeline each time an instruction is routed to the first pipeline, and the counter logic is further arranged to increment the second counter responsive to that indication. Synchronisation logic is then provided which is arranged, when an instruction is in the retirement stage of the second pipeline, to determine with reference to the values of the first and second counters whether that instruction can be retired. If so, the retirement stage is arranged to cause an update of a state of the data processing apparatus dependent on the result of execution of that instruction.
摘要翻译： 本发明提供了一种用于使被配置为执行指令序列的处理器的第一流水线和第二流水线同步的装置和方法。 处理器被布置为依赖于预定标准来通过第一或第二流水线顺序地路由指令，每个流水线具有包括退休阶段的多个流水线阶段。 计数器逻辑被提供用于维持与第一流水线相关的第一计数器和与第二流水线相关的第二计数器。 对于第一流水线中的每个指令，确定何时该指令到达该指令的异常状态的第一流水线内的一个点，并且该计数器逻辑被布置成响应于这种确定来增加第一计数器。 处理器被布置为在每次将指令路由到第一流水线时在第二流水线内产生指示，并且计数器逻辑还被布置为响应于该指示递增第二计数器。 然后提供同步逻辑，当指令处于第二流水线的退休阶段时，其被配置为参考第一和第二计数器的值来确定该指令是否可以退休。 如果是这样，退休阶段被安排为依赖于该指令的执行结果来更新数据处理装置的状态。
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公开(公告)号：US06976126B2
公开(公告)日：2005-12-13
申请号：US10384771
申请日：2003-03-11
CPC分类号： G06F12/0864 , Y02D10/13
摘要： The present invention provides an apparatus and method for accessing data values in a cache and in particular accessing data values in an ‘n’ way set associative cache. A data processing apparatus is provided comprising an ‘n’ way set-associative cache, each cache way having a plurality of entries for storing a corresponding plurality of data values. A cache controller is provided which is operable on receipt of an access request for a data value to determine whether that data value is accessible within the cache, the cache comprising cache access logic operable under the control of the cache controller to determine whether a data value the subject of an access request is accessible in one of the cache ways. Also provided is a way lookup cache arranged to store an indication of the cache way in which a number of the plurality of data values stored in the cache are accessible. The cache controller is operable, when an access request for a data value specifies a non-sequential access, to reference the way lookup cache to determine whether that data value is identified in the way lookup cache and, if so, the cache controller being further operable to suppress the operation of the cache access logic and to cause that data value to be accessed. The provision of a way lookup cache enables the power consumption of the cache to be reduced by enabling the operation of the cache access logic to be suppressed.
摘要翻译： 本发明提供一种用于访问高速缓存中的数据值的装置和方法，特别是以“n”方式组合关联高速缓存访问数据值。 提供了一种数据处理装置，其包括“n”路组合关联高速缓存，每个高速缓存路径具有用于存储对应的多个数据值的多个条目。 提供了一种高速缓存控制器，其可在接收到数据值的访问请求时操作以确定该高速缓存中是否可访问该数据值，该高速缓存包括在高速缓存控制器的控制下可操作的高速缓存访问逻辑，以确定数据值 访问请求的主题可以以缓存方式之一访问。 还提供了一种方式查找缓存器，其被布置为存储其中存储在高速缓存中的多个数据值的数量可访问的高速缓存方式的指示。 当对数据值的访问请求指定非顺序访问时，高速缓存控制器可操作地参考查找缓存的方式来确定该查找高速缓存是否识别该数据值，并且如果是，则高速缓存控制器进一步 可操作地抑制高速缓存访问逻辑的操作并使得该数据值被访问。 提供方式查找高速缓存使得能够抑制高速缓存访问逻辑的操作来降低高速缓存的功耗。
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