公开(公告)号：US20110213934A1

公开(公告)日：2011-09-01

申请号：US12659234

申请日：2010-03-01

申请人： Peter Richard Greenhalgh ,  Richard Roy Grisenthwaite

发明人： Peter Richard Greenhalgh ,  Richard Roy Grisenthwaite

IPC分类号： G06F15/76 ,  G06F12/08 ,  G06F9/02

CPC分类号： G06F9/5088 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D10/32 ,  Y02D50/20

摘要： A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. In addition, the switch controller masks predetermined processor specific configuration information from the at least one operating system such that the transfer of the workload is transparent to that operating system. Such an approach has been found to yield significant energy consumption benefits whilst avoiding complexities associated with providing operating systems with the capability for switching applications between processing circuits.

摘要翻译： 提供一种用于在两个处理电路之间切换工作负载的性能的数据处理装置和方法。 该数据处理装置具有与第二处理电路架构上兼容的第一处理电路，但第一处理电路在微架构上不同于第二处理电路。 在任何时间点，由至少一个应用程序和用于运行该应用程序的至少一个操作系统组成的工作负载由第一处理电路和第二处理电路之一执行。 开关控制器响应于传送刺激来执行切换操作以将工作负载的性能从源处理电路传送到目的地处理电路，源处理电路是第一和第二处理电路之一，目的地处理电路是 第一和第二处理电路中的另一个。 在切换操作期间，交换机控制器使得源处理电路使其当前架构状态可用于目的地处理电路，当前架构状态是在切换操作开始时该共享存储器不可用的状态，即 目的地处理电路必须成功地从源处理电路接管工作负载的性能。 另外，交换机控制器从至少一个操作系统屏蔽预定的处理器特定配置信息，使得工作负载的传输对该操作系统是透明的。 已经发现这种方法产生显着的能量消耗益处，同时避免了与提供操作系统相关联的复杂性，其具有在处理电路之间切换应用的能力。

公开(公告)号：US08418187B2

公开(公告)日：2013-04-09

申请号：US12659234

申请日：2010-03-01

申请人： Peter Richard Greenhalgh ,  Richard Roy Grisenthwaite

发明人： Peter Richard Greenhalgh ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/50

CPC分类号： G06F9/5088 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D10/32 ,  Y02D50/20

摘要： A data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being miero-architccturally different from the second processing circuitry. A switch controller performs a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry and is necessary for the destination processing circuitry to successfully lake over performance of the workload from the source processing circuitry. The switch controller masks predetermined processor specific configuration information such that the transfer of the workload is transparent to that operating system.

摘要翻译： 数据处理装置具有在结构上与第二处理电路兼容的第一处理电路，但是第一处理电路与第二处理电路具有不同的结构。 开关控制器执行切换操作以将工作负载的性能从源处理电路传送到目的地处理电路，源处理电路是第一和第二处理电路之一，目的地处理电路是第一和第二处理中的另一个 电路。 在切换操作期间，交换机控制器使得源处理电路使得目前处理电路可用的当前体系结构状态，并且对于目的地处理电路来说，成功地从源处理电路中对工作负载的性能成功过滤是必要的。 交换机控制器屏蔽预定的处理器特定配置信息，使得工作负载的传输对于该操作系统是透明的。

公开(公告)号：US20110213935A1

公开(公告)日：2011-09-01

申请号：US12659235

申请日：2010-03-01

申请人： Peter Richard Greenhalgh ,  Richard Roy Grisenthwaite

发明人： Peter Richard Greenhalgh ,  Richard Roy Grisenthwaite

IPC分类号： G06F15/76 ,  G06F12/08 ,  G06F9/02

CPC分类号： G06F1/3203 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22

摘要： A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. The switch controller is arranged, during the handover operation, to cause the source processing circuitry to make its current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory shared between the first and second processing circuitry at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. Further, the source processing circuitry and second processing circuitry implement an accelerated mechanism to make the current architectural state available to the destination processing circuitry without routing of the current architectural state via the shared memory. Since the accelerated mechanism is quick and energy efficient, it increases the number of situations it which it is energy efficient to make the switch from one processing circuitry to the other.

公开(公告)号：US09075622B2

公开(公告)日：2015-07-07

申请号：US12010318

申请日：2008-01-23

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3875 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3861

摘要： In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded, each block representing a portion of an instruction. Pre-decoding circuitry is configured to perform pre-decoding operations on the blocks. For at least one portion of an instruction from the first set of instructions and at least one portion of an instruction from the second set of instructions the pre-decoding operation performed on a block fetched from memory is independent of whether the block is identified as representing the at least one portion of an instruction from the first set of instructions or as the at least one portion of an instruction from the second set of instructions.

公开(公告)号：US07925866B2

公开(公告)日：2011-04-12

申请号：US12314095

申请日：2008-12-03

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske ,  Max Zardini

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske ,  Max Zardini

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3861

摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

公开(公告)号：US07917735B2

公开(公告)日：2011-03-29

申请号：US12010316

申请日：2008-01-23

申请人： Peter Richard Greenhalgh

发明人： Peter Richard Greenhalgh

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3853

摘要： A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in a cache for access by processing circuitry. For a first set of instructions, each instruction comprises a plurality of instruction portions, and the pre-decoding circuitry generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions. If when applying the pre-decoding operation to an instruction in the first set, the pre-decoding circuitry does not have access to all of the plurality of instruction portions of that instruction, the pre-decoding circuitry is arranged to provide in association with at least one pre-decoded instruction portion that it does generate, an indication that the pre-decoded instruction portion relates to an incomplete pre-decoding operation. This provides a simple and effective mechanism for detecting situations where a pre-decoded instruction as later read from the cache may have become corrupted by the pre-decoding operation, and accordingly should not be relied upon.

摘要翻译： 提供了用于对指令进行解码的数据处理装置和方法。 数据处理装置具有预解码电路，用于接收从存储器取出的指令，并用于执行预解码操作，以产生相应的预解码指令，然后存储在高速缓存中以供处理电路访问。 对于第一组指令，每个指令包括多个指令部分，并且预解码电路生成包括多个预解码指令部分的对应的预解码指令。 如果当将预解码操作应用于第一组中的指令时，预解码电路不具有对该指令的所有多个指令部分的访问权，则预解码电路被布置为提供与在 其确实生成的至少一个预解码指令部分，预解码指令部分与不完整的预解码操作有关的指示。 这提供了一种用于检测其中稍后从缓存读取的预解码指令可能已经被预解码操作损坏的情况的简单且有效的机制，因此不应被依赖。

公开(公告)号：US07747839B2

公开(公告)日：2010-06-29

申请号：US12010305

申请日：2008-01-23

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3861

摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

公开(公告)号：US20110213993A1

公开(公告)日：2011-09-01

申请号：US12659230

申请日：2010-03-01

申请人： Peter Richard Greenhalgh

发明人： Peter Richard Greenhalgh

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F1/32

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/5094 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/122 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.

摘要翻译： 响应于传输刺激，处理工作负载的性能从源处理电路传送到目的地处理电路，以准备将源处理电路置于转移之后的省电状态。 为了减少转移之后目的地处理电路所需的存储器获取数量，源处理电路的高速缓存保持在用于窥探期的供电状态。 在窥探期间，缓存窥探电路监听源缓存中的数据值，并检索目标处理电路的窥探数据值。

公开(公告)号：US20090187743A1

公开(公告)日：2009-07-23

申请号：US12010313

申请日：2008-01-23

申请人： Peter Richard Greenhalgh

发明人： Peter Richard Greenhalgh

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3865

摘要： The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing circuitry. For each instruction fetched from the memory, the pre-decoding circuitry detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.

摘要翻译： 本发明提供了一种数据处理装置，包括用于执行指令序列的处理电路和用于接收从存储器取出的指令的预解码电路。 预解码电路执行预解码操作以产生相应的预解码指令，并将其存储在高速缓存中以供处理电路访问。 对于从存储器取出的每个指令，预解码电路检测指令是否是异常指令，并且在这种检测时，与相应的预解码指令相关联地提供标识该指令为异常的标识符。

公开(公告)号：US20090187742A1

公开(公告)日：2009-07-23

申请号：US12010312

申请日：2008-01-23

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske

IPC分类号： G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3865

摘要： A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.

摘要翻译： 数据处理装置设置有用于产生存储在指令高速缓存20中的预解码指令的预解码电路10.来自指令高速缓存20的预解码指令由解码电路45,50,46读取并使用 以形成用于控制与预解码指令相对应的处理操作的控制信号。 最初提取的程序指令可以属于多个指令集中的相应的指令集。 来自一个指令集的指令由预解码电路10预解码为具有共享格式的预解码指令，以表示从另一个指令集获取的相应指令的共享功能。 以这种方式，解码电路的共享部分可以相对于来自这两个不同指令集的指令的共享功能产生控制信号。