公开(公告)号：US06976126B2

公开(公告)日：2005-12-13

申请号：US10384771

申请日：2003-03-11

申请人： Christopher Michael Clegg ,  Richard Roy Grisenthwaite

发明人： Christopher Michael Clegg ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0864 ,  Y02D10/13

摘要： The present invention provides an apparatus and method for accessing data values in a cache and in particular accessing data values in an ‘n’ way set associative cache. A data processing apparatus is provided comprising an ‘n’ way set-associative cache, each cache way having a plurality of entries for storing a corresponding plurality of data values. A cache controller is provided which is operable on receipt of an access request for a data value to determine whether that data value is accessible within the cache, the cache comprising cache access logic operable under the control of the cache controller to determine whether a data value the subject of an access request is accessible in one of the cache ways. Also provided is a way lookup cache arranged to store an indication of the cache way in which a number of the plurality of data values stored in the cache are accessible. The cache controller is operable, when an access request for a data value specifies a non-sequential access, to reference the way lookup cache to determine whether that data value is identified in the way lookup cache and, if so, the cache controller being further operable to suppress the operation of the cache access logic and to cause that data value to be accessed. The provision of a way lookup cache enables the power consumption of the cache to be reduced by enabling the operation of the cache access logic to be suppressed.

摘要翻译： 本发明提供一种用于访问高速缓存中的数据值的装置和方法，特别是以“n”方式组合关联高速缓存访​​问数据值。 提供了一种数据处理装置，其包括“n”路组合关联高速缓存，每个高速缓存路径具有用于存储对应的多个数据值的多个条目。 提供了一种高速缓存控制器，其可在接收到数据值的访问请求时操作以确定该高速缓存中是否可访问该数据值，该高速缓存包括在高速缓存控制器的控制下可操作的高速缓存访​​问逻辑，以确定数据值 访问请求的主题可以以缓存方式之一访问。 还提供了一种方式查找缓存器，其被布置为存储其中存储在高速缓存中的多个数据值的数量可访问的高速缓存方式的指示。 当对数据值的访问请求指定非顺序访问时，高速缓存控制器可操作地参考查找缓存的方式来确定该查找高速缓存是否识别该数据值，并且如果是，则高速缓存控制器进一步 可操作地抑制高速缓存访​​问逻辑的操作并使得该数据值被访问。 提供方式查找高速缓存使得能够抑制高速缓存访​​问逻辑的操作来降低高速缓存的功耗。

公开(公告)号：US09477834B2

公开(公告)日：2016-10-25

申请号：US13368419

申请日：2012-02-08

申请人： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

发明人： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

IPC分类号： G06F21/52 ,  G06F9/30 ,  G06F9/46

CPC分类号： G06F21/52 ,  G06F9/30134 ,  G06F9/462 ,  G06F21/6245 ,  G06F2221/2105

摘要： A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.

摘要翻译： 一种数据处理装置，包括用于执行数据处理的电路，多个寄存器; 以及包括具有不同安全级别的区域的数据存储器，至少一个安全区域（用于存储由安全域中操作的数据处理电路可访问并且不能由不安全域中操作的数据处理电路访问的敏感数据）和少于 安全区域（用于存储较不安全的数据）。 电路被配置为响应于正在执行的程序代码的存储位置来确定将数据存储到数据或从其加载数据。 响应于调用要执行的功能的程序代码，存储在第二区域中的功能代码，第二区域具有与第一区域不同的安全级别，数据处理电路被配置为确定第一和第二区域中的哪一个 具有较低的安全级别。

公开(公告)号：US08856408B2

公开(公告)日：2014-10-07

申请号：US12923723

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/362 ,  G06F13/364 ,  G06F13/16

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.

摘要翻译： 互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，该电路包括用于接收交易请求的至少一个输入; 用于输出交易请求的至少一个输出; 用于在输入和输出之间传送事务请求的至少一个路径。 响应于屏障事务请求，控制电路将接收的事务请求从输入路由到输出。 通过不允许对至少一些交易请求进行重新排序，关于通过所述至少一个路径中的一个路径的事务请求流中的屏障事务请求来维护至少一些事务请求的排序。 控制电路包括响应信号发生器，响应信号发生器响应于接收到屏障事务请求以发出响应信号。

公开(公告)号：US08788775B2

公开(公告)日：2014-07-22

申请号：US13067812

申请日：2011-06-28

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F12/145 ,  G06F9/30145 ,  G06F9/30189 ,  G06F2212/1004

摘要： A data processing system 2 including processing circuitry 4 operating in either a first mode or a second mode. Page table data 30 including access control bits 40, 42, is used to control permissions for memory access to memory pages. In the first mode, the access control bits include at least one instance of a redundant encoding. In the second mode, the redundant encoding is removed to provide more efficient use of the access control bit encoding space.

摘要翻译： 数据处理系统2包括以第一模式或第二模式操作的处理电路4。 包括访问控制位40,42的页表数据30用于控制对存储器页的存储器访问的许可。 在第一模式中，访问控制位包括冗余编码的至少一个实例。 在第二模式中，去除冗余编码以提供更有效地使用访问控制位编码空间。

公开(公告)号：US08301856B2

公开(公告)日：2012-10-30

申请号：US12656786

申请日：2010-02-16

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F12/14

CPC分类号： G06F12/1491 ,  G06F21/52 ,  G06F21/74 ,  G06F21/79 ,  G06F2221/2105

摘要： An apparatus for processing data 2 includes a processor 8, a memory 6 and memory control circuitry 12. The processor 8 operates in a plurality of hardware modes including a privileged mode and a user mode. When operating in the privileged mode, the processor 8 is blocked by the memory control circuitry 12 from fetching instructions from memory address regions 34, 38, 42 within the memory 6 which are writeable within the user mode if a security flag within register 46 is set to indicate that this blocking mechanism is active.

摘要翻译： 处理数据2的装置包括处理器8，存储器6和存储器控制电路12.处理器8以包括特权模式和用户模式的多种硬件模式操作。 当在特权模式下操作时，处理器8被存储器控制电路12阻止从存储器6中的存储器地址区域34,38,42中获取指令，这些指令可在用户模式内写入，如果寄存器46内的安全标志被设置 以指示该阻塞机制是活动的。

公开(公告)号：US20120089817A1

公开(公告)日：2012-04-12

申请号：US13200348

申请日：2011-09-23

申请人： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

发明人： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC分类号： G06F9/30

CPC分类号： G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and then conditionally select either that register or a further register on which no operation has been performed. The apparatus comprises an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register; a data processor configured to perform data processing operations controlled by the instruction decoder wherein: the data processor is responsive to the decoded at least one conditional select instruction and the condition having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register; and the data processor is responsive to the decoded at least one conditional select instruction and the condition not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

摘要翻译： 一种数据处理装置，方法和计算机程序，其对诸如寄存器的一个数据元素执行操作，然后有条件地选择该寄存器或其上没有进行任何操作的另外的寄存器。 该装置包括：指令解码器，被配置为对至少一个条件选择指令进行解码，所述至少一个条件选择指令指定主源寄存器，次源寄存器，目的地寄存器，条件以及对数据执行的操作 来自次级源寄存器的元件; 配置为执行由指令解码器控制的数据处理操作的数据处理器，其中：数据处理器响应于解码的至少一个条件选择指令和具有预定结果的条件，以从次级源寄存器对数据元素执行操作 以形成结果数据元素并将结果数据元素存储在目的寄存器中; 并且数据处理器响应于解码的至少一个条件选择指令和不具有预定结果的条件，以从主寄存器的数据元素形成结果数据元素，并将结果数据元素存储在目的寄存器中。

公开(公告)号：US08051271B2

公开(公告)日：2011-11-01

申请号：US12216253

申请日：2008-07-01

申请人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/1036

摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.

摘要翻译： 公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。 地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目 存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

公开(公告)号：US20110225389A1

公开(公告)日：2011-09-15

申请号：US13064243

申请日：2011-03-14

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/1009 ,  G06F2212/651

摘要： Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables 28, 32, 36, 38, 40, 42. A page size variable S is used to control the memory address translation circuitry 14 to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 62.

摘要翻译： 存储器地址转换电路14执行自顶向下的页面行进操作，以使用存储在转换表28,32,36,38,40,40的层级中的转换数据将虚拟存储器地址VA转换为物理存储器地址PA。页面 大小变量S用于控制存储器地址转换电路14以不同尺寸的物理存储器地址页面，虚拟存储器地址和转换表的页面进行操作。 这些不同的大小可以是所有4 kB或全部64 kB。 该系统可以支持多个虚拟机执行环境。 这些虚拟机执行环境可以独立地设置自己的页面大小变量，以及相关联的管理程序62的页面大小。

公开(公告)号：US07870437B2

公开(公告)日：2011-01-11

申请号：US11984221

申请日：2007-11-14

申请人： Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite ,  Michael John Williams

发明人： Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite ,  Michael John Williams

IPC分类号： G06F11/00

CPC分类号： G06F11/3476 ,  G06F11/348 ,  G06F2201/865

摘要： A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications.

摘要翻译： 提供了一种数据处理装置，包括用于执行活动的被监测电路，用于产生表示这些活动中的至少一些的微量元素流的跟踪电路，以及检测电路，用于检测所述活动的预定子集的发生 电路正在产生微量元素。 当检测到该预定活动子集中的活动时，将定时指示添加到微量元素流。 因此，可以通过将跟踪流中添加定时指示的跟踪元素限制到生成微量元素的活动的预定子集，并将有价值的全局或相对定时精度保留在有价值的跟踪带宽中 在跟踪流中表示的那些活动被保留，而不会使跟踪流与时间指示淹没。

公开(公告)号：US07793078B2

公开(公告)日：2010-09-07

申请号：US11095655

申请日：2005-04-01

申请人： Matthew Paul Elwood ,  David John Butcher ,  Richard Roy Grisenthwaite

发明人： Matthew Paul Elwood ,  David John Butcher ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/30

CPC分类号： G06F9/3806 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3844

摘要： A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.

摘要翻译： 数据处理系统可在第一状态下操作，以使用具有第一指令集编码的第一指令集。 数据处理系统还可在第二状态下操作以使用具有第二指令编码的第二指令集。 在两个不同的指令集中提供的条件转移指令被设置为使用相同的指令编码。