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    Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same
    72.
    发明授权
    Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same 有权
    具有由导电图案限定的气隙间隔物的集成电路器件及其制造方法

    公开(公告)号：US09331072B2

    公开(公告)日：2016-05-03

    申请号：US14165721

    申请日：2014-01-28

    Applicant: Kang-Ill Seo ,  Jin-Wook Lee

    Inventor： Kang-Ill Seo ,  Jin-Wook Lee

    IPC: H01L27/088 ,  H01L23/485 ,  H01L21/8234

    CPC classification number: H01L29/7851 ,  H01L21/823468 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.

    Abstract translation: 提供具有空腔的集成电路器件和制造集成电路器件的方法。 集成电路器件可以包括限定凹部的一对间隔件。 集成电路器件还可以包括凹陷中的下导电图案和下导电图案上的上导电图案。 上导电图案可以具有相对于下导电图案的蚀刻选择性，并且可以暴露邻近上导电图案的侧壁的下导电图案的上表面。 一对间隔物中的一个的内侧壁，下导电图案的上表面和上导电图案的侧壁可以限定空间，并且可以在上导电图案上形成封盖图案，以密封上导电图案的顶部 空间，使得空腔设置在封盖图案下方。

    Method of reading data in non-volatile memory device
    74.
    发明授权
    Method of reading data in non-volatile memory device 有权
    在非易失性存储器件中读取数据的方法

    公开(公告)号：US08321765B2

    公开(公告)日：2012-11-27

    申请号：US12702481

    申请日：2010-02-09

    Applicant: Jin-Wook Lee ,  Sang-Won Hwang

    Inventor： Jin-Wook Lee ,  Sang-Won Hwang

    IPC: G11C29/00

    CPC classification number: G06F11/1068 ,  G11C16/26 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/19

    Abstract: In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.

    Abstract translation: 在从非易失性存储器件读取数据的方法中，基于字线电压生成读取数据。 读取数据包括从包括在非易失性存储器件中的多个扇区读取的数据。 基于读取数据和坏扇区信息传输数据不良扇区数据。 坏扇区数据对应于从包括在多个扇区中的至少一个坏扇区读取的数据。 通过检查坏扇区数据的错误位来更新坏扇区信息。 基于更新的坏扇区信息生成字线电压。

    Flash memory device with split string selection line structure
    77.
    发明授权
    Flash memory device with split string selection line structure 有权
    闪存设备具有分割字符串选择线结构

    公开(公告)号：US07817473B2

    公开(公告)日：2010-10-19

    申请号：US12014902

    申请日：2008-01-16

    Applicant: Jin-Wook Lee ,  Sang-Won Hwang

    Inventor： Jin-Wook Lee ,  Sang-Won Hwang

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C16/24 ,  G11C16/3427

    Abstract: A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the plurality of strings includes a plurality of memory cells series connected between a string select transistor and a ground select transistor. The flash memory device also includes a plurality of string selection lines, wherein each one of the plurality of string selection lines is respectively connected to string select transistors associated the plurality of strings in one of the plurality of sectors.

    Abstract translation: 闪存器件被公开并且包括包括多个扇区的存储单元阵列。 多个扇区中的每一个包括多个串，并且多个串中的每一个包括连接在串选择晶体管和接地选择晶体管之间的多个存储单元串联。 闪存装置还包括多个串选择线，其中多个串选择线中的每一个分别连接到与多个扇区中的一个扇区中的多个扇区中的多个字符串相关联的串选择晶体管。

    METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE
    78.
    发明申请
    METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE 有权
    在非易失性存储器件中读取数据的方法

    公开(公告)号：US20100211852A1

    公开(公告)日：2010-08-19

    申请号：US12702481

    申请日：2010-02-09

    Applicant: Jin-Wook Lee ,  Sang-Won Hwang

    Inventor： Jin-Wook Lee ,  Sang-Won Hwang

    IPC: H03M13/05 ,  G11C16/04 ,  G11C16/06 ,  G06F11/10 ,  H03M13/19 ,  H03M13/07

    CPC classification number: G06F11/1068 ,  G11C16/26 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/19

    Abstract: In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.

    Abstract translation: 在从非易失性存储器件读取数据的方法中，基于字线电压生成读取数据。 读取数据包括从包括在非易失性存储器件中的多个扇区读取的数据。 基于读取数据和坏扇区信息传输数据不良扇区数据。 坏扇区数据对应于从包括在多个扇区中的至少一个坏扇区读取的数据。 通过检查坏扇区数据的错误位来更新坏扇区信息。 基于更新的坏扇区信息生成字线电压。

    Flash memory device and method of programming flash memory device
    79.
    发明授权
    Flash memory device and method of programming flash memory device 有权
    闪存设备和闪存设备编程方法

    公开(公告)号：US07746703B2

    公开(公告)日：2010-06-29

    申请号：US12126080

    申请日：2008-05-23

    Applicant: Kyong-Ae Kim ,  Jin-Wook Lee ,  Yun-Ho Choi

    Inventor： Kyong-Ae Kim ,  Jin-Wook Lee ,  Yun-Ho Choi

    IPC: G11C11/34 ,  G11C16/06

    CPC classification number: G11C16/349

    Abstract: A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.

    Abstract translation: 闪速存储器件及其编程方法包括存储单元阵列，通过/失败校验电路和控制逻辑电路。 存储单元阵列包括以行和列排列的多个存储单元。 通过/失败检查电路验证在列扫描操作期间由列地址选择的数据位是否具有程序数据值。 控制逻辑电路根据所选数据位检测故障数据位，并响应于通过/不通过检查电路的验证结果存储列地址。 控制逻辑电路还将多个故障数据位与参考值进行比较，并根据比较结果控制列地址的生成。

    Flash memory data storage apparatus
    80.
    发明授权
    Flash memory data storage apparatus 有权
    闪存数据存储装置

    公开(公告)号：US07467251B2

    公开(公告)日：2008-12-16

    申请号：US11224662

    申请日：2005-09-12

    Applicant: Min-Gun Park ,  Jin-Wook Lee

    Inventor： Min-Gun Park ,  Jin-Wook Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/14

    CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/1689

    Abstract: A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i−l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i−1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.

    Abstract translation: 闪存数据存储装置包括闪存和闪存接口。 闪存通过闪存总线组收发数据。 闪存接口包括第一至第n个闪存输入缓冲器，其响应于第一至第n个传输时钟控制信号将数据分阶段地传送到主机总线组。 至少第一个闪存输入缓冲器通过第i个输入缓冲区总线组提供数据。 第i个输入缓冲器总线组中的每一个的总线宽度比第（i-1）个输入缓冲器总线组中的每一个的总线宽度宽。 第i个传送时钟控制信号的周期比第（i-1）个传输时钟控制信号的周期长。 通过将闪存总线组的总线宽度除以每个第i个输入缓冲器总线组的总线宽度来划分闪存总线组的总线宽度来获得Ni。

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