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    Nonvolatile memory device and method of manufacturing the same
    71.
    发明申请
    Nonvolatile memory device and method of manufacturing the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20090121277A1

    公开(公告)日：2009-05-14

    申请号：US12289297

    申请日：2008-10-24

    申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

    发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

    摘要： The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

    摘要翻译： 非易失性存储器件包括半导体衬底和限定半导体衬底中的有源区的器件隔离层。 器件隔离层包括比半导体衬底的顶表面低的顶表面，使得有源区的侧上表面被暴露。 感测线与有源区和器件隔离层交叉，并且与感测线间隔开的字线与有源区和器件隔离层交叉。

    Non-volatile memory device
    72.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US07512003B2

    公开(公告)日：2009-03-31

    申请号：US11789003

    申请日：2007-04-23

    申请人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

    发明人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

    摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

    摘要翻译： 非易失性存储器件包括存储器单元块，第一切换块和第二切换块。 多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管 它连接到源线。 第一切换块选择性地将全局位线连接到本地位线，而第二切换块以预定位数为单位来控制存储单元块中的存储单元。 第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

    SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    73.
    发明申请
    SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    分离门型非易失性存储器件及其制造方法

    公开(公告)号：US20080318406A1

    公开(公告)日：2008-12-25

    申请号：US12194202

    申请日：2008-08-19

    申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

    发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.

    摘要翻译： 在分闸式非易失存储器件及其制造方法中， 辅助层图案设置在半导体衬底的源极区域上。 由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。 因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME
    74.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    非易失性存储器件及其形成方法

    公开(公告)号：US20080266981A1

    公开(公告)日：2008-10-30

    申请号：US12173742

    申请日：2008-07-15

    申请人： KWANG WOOK KOH ,  Jeong-Uk Han

    发明人： KWANG WOOK KOH ,  Jeong-Uk Han

    IPC分类号： G11C11/34 ,  H01L29/788

    CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7885

    摘要： A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

    摘要翻译： 非易失性存储器件包括形成在半导体衬底中的第一和第二杂质扩散区，以及形成在第一和第二杂质扩散区之间的半导体衬底的沟道区上的存储单元。 存储单元包括形成在沟道区上的堆叠栅极结构，以及形成在堆叠栅极结构的沟道区和相对侧壁上的第一和第二选择栅。 由于第一选择栅极和第二选择栅极是间隔形状以在层叠栅极结构的相对侧壁上自对准，所以减小了存储单元的尺寸以增强半导体器件的集成密度。

    Methods of forming split-gate non-volatile memory cells including raised oxide layers on field oxide regions
    75.
    发明授权
    Methods of forming split-gate non-volatile memory cells including raised oxide layers on field oxide regions 失效
    在场氧化物区域上形成包括凸起的氧化物层的分裂非晶体非易失性存储单元的方法

    公开(公告)号：US07351636B2

    公开(公告)日：2008-04-01

    申请号：US11138702

    申请日：2005-05-26

    申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

    发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7885

    摘要： A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxide region, the oxide layer electrically isolates the first and second adjacent floating gates from one another. A control gate is formed on the oxide layer on the first and second adjacent floating gates. Related devices are also disclosed.

    摘要翻译： 形成分闸非易失性存储单元的方法可以包括形成与其之间的场氧化物区域自对准的第一和第二相邻浮置栅极。 形成覆盖第一和第二相邻浮动栅极和场氧化物区域的氧化物层，氧化物层将第一和第二相邻浮栅彼此电隔离。 控制栅极形成在第一和第二相邻浮动栅极上的氧化物层上。 还公开了相关设备。

    Nonvolatile memory devices
    77.
    发明授权
    Nonvolatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US07183157B2

    公开(公告)日：2007-02-27

    申请号：US10867152

    申请日：2004-06-14

    申请人： Tae-Kwang Yoo ,  Jeong-Uk Han

    发明人： Tae-Kwang Yoo ,  Jeong-Uk Han

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

    摘要： Nonvolatile memory devices and methods for fabricating the same are provided. The device includes first and second base patterns disposed under floating and selection gates, respectively, at an active region. A channel region is formed in the active region between the first and second base patterns, and source and drain regions are formed in the active region adjacent to the first and second base patterns, respectively. The method includes forming first and second base patterns on a semiconductor substrate to be separated from each other by a predetermined space. A channel region is formed in the semiconductor substrate between the first and second base patterns. Source and drain regions are formed in the semiconductor substrate adjacent to the reverse side of the channel region on the basis of the first and second base patterns, respectively. A tunnel oxide layer is formed on a predetermined region of the channel region. A memory gate is formed to cover the first base pattern and the tunnel oxide layer. A selection gate pattern is then formed to cover the second base pattern.

    摘要翻译： 提供非易失性存储器件及其制造方法。 该装置包括分别设置在有源区域的浮动选择栅极下的第一和第二基本图案。 在第一和第二基底图案之间的有源区中形成沟道区，并且分别在与第一和第二基底图案相邻的有源区中形成源极和漏极区。 该方法包括在半导体衬底上形成第一和第二基底图案以彼此分开预定的空间。 在第一和第二基底图案之间的半导体衬底中形成沟道区。 源区和漏区分别基于第一和第二基底图案形成在与沟道区的相反侧相邻的半导体衬底中。 隧道氧化层形成在沟道区的预定区域上。 形成存储栅极以覆盖第一基底图案和隧道氧化物层。 然后形成选择栅极图案以覆盖第二基底图案。

    Nonvolatile memory devices and methods of forming the same
    78.
    发明申请
    Nonvolatile memory devices and methods of forming the same 审中-公开
    非易失存储器件及其形成方法

    公开(公告)号：US20060071265A1

    公开(公告)日：2006-04-06

    申请号：US11232284

    申请日：2005-09-21

    申请人： Kwang-Wook Koh ,  Jeong-Uk Han

    发明人： Kwang-Wook Koh ,  Jeong-Uk Han

    IPC分类号： H01L21/8238 ,  H01L29/788

    CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7885

    摘要： A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

    摘要翻译： 非易失性存储器件包括形成在半导体衬底中的第一和第二杂质扩散区，以及形成在第一和第二杂质扩散区之间的半导体衬底的沟道区上的存储单元。 存储单元包括形成在沟道区上的堆叠栅极结构，以及形成在堆叠栅极结构的沟道区和相对侧壁上的第一和第二选择栅。 由于第一选择栅极和第二选择栅极是间隔形状以在层叠栅极结构的相对侧壁上自对准，所以减小了存储单元的尺寸以增强半导体器件的集成密度。