-
公开(公告)号：US08445345B2
公开(公告)日：2013-05-21
申请号：US13227750
申请日：2011-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L29/51 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L29/49 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7833
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
摘要翻译： 形成具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构的方法包括在半导体衬底上形成第一晶体管器件和第二晶体管器件。 第一晶体管器件和第二晶体管器件最初具有牺牲性虚拟栅极结构。 去除牺牲虚拟栅极结构，并且为第一晶体管器件选择性地形成一组垂直氧化物间隔物。 垂直氧化物间隔物组与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。
-
72.发明申请MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION 有权具有半导体通道的MOSFET和具有增强结隔离的嵌入式压电器和制造方法公开(公告)号：US20130105818A1
公开(公告)日：2013-05-02
申请号：US13283308
申请日：2011-10-27
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译： 场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。 嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。 此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。
-
公开(公告)号：US08362560B2
公开(公告)日：2013-01-29
申请号：US12816697
申请日：2010-06-16
IPC分类号： H01L27/12
CPC分类号： H01L29/66045 , H01L21/26506 , H01L21/84 , H01L27/105 , H01L27/1203 , H01L29/6656 , H01L29/66628 , H01L29/66659
摘要： Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.
摘要翻译： 本发明的实施例提供了制造具有类似物理尺寸但由于不同有效通道长度而具有不同操作特性的装置的能力。 通过在栅极和至少一个源极或漏极的边界处形成突变结点来控制有效沟道长度。 突变结在退火过程中影响扩散，这又控制有效沟道长度，允许同一芯片上物理上相似的器件具有不同的工作特性。
-
公开(公告)号：US20130015534A1
公开(公告)日：2013-01-17
申请号：US13184537
申请日：2011-07-16
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7854
摘要： A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.
摘要翻译： 一种三维FET器件结构，其包括多个三维FET器件。 三维FET器件中的每一个包括绝缘基底，垂直于绝缘基底取向的三维鳍片，围绕三维翅片缠绕的栅极电介质和围绕栅极电介质缠绕并垂直于三维翅片延伸的栅极， 具有将器件宽度定义为与栅极电介质接触的三维鳍片的圆周的三维鳍片。 三维FET器件中的至少一个具有第一器件宽度，而三维FET器件中的至少一个具有第二器件宽度。 第一个设备宽度与第二个设备宽度不同。 还包括制造三维FET器件结构的方法。
-
公开(公告)号：US20120329232A1
公开(公告)日：2012-12-27
申请号：US13602644
申请日：2012-09-04
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/823418 , H01L21/823425 , H01L21/84 , H01L29/66628
摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.
摘要翻译： 在本发明的一个示例性实施例中，半导体结构包括：衬底; 以及至少部分地覆盖所述衬底的多个器件，其中所述多个器件包括经由具有第一长度的第一升高源极/漏极耦合到第二器件的第一器件，其中所述第一器件进一步耦合到第二升高源 /漏极，其中第一器件包括晶体管，其中第一升高源极/漏极和第二升高源极/漏极至少部分地超过衬底，其中第二升高源极/漏极包括端子电接触，其中 第二长度大于第一长度。
-
公开(公告)号：US20120299075A1
公开(公告)日：2012-11-29
申请号：US13568601
申请日：2012-08-07
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背面带的至少第一部分位于掺杂部分的下面，背侧带在背面带的第一端和电容器处耦合到顶部硅层的掺杂部分 在背面带的第二端; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。
-
公开(公告)号：US20120286329A1
公开(公告)日：2012-11-15
申请号：US13106900
申请日：2011-05-13
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body.
摘要翻译： 公开了与应变体UTSOI FET器件有关的方法和结构。 该方法包括在源极/漏极区域中形成穿透绝缘层下方的衬底中的空隙。 空隙被外延填充有与SOI层不同的晶格常数的半导体材料，因此成为应力块，并且在FET器件本体上施加应变。
-
公开(公告)号：US20120276695A1
公开(公告)日：2012-11-01
申请号：US13098352
申请日：2011-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845
摘要： A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.
摘要翻译： 公开了一种方法，其特征在于用于超薄平面和FinFET CMOS器件的凸起源极/漏极和应变体的处理集成。 NFET和PFET器件通过用于PFET器件的原位p型掺杂SiGe的选择性外延以及用于NFET器件的原位n型掺杂Si：C来提高其源极/漏极。 这种升高的源极/漏极提供低的寄生电阻，并且它们对于相应的载流子，电子或空穴，迁移率增强赋予了正确符号的器件体上的应变。
-
公开(公告)号：US20120267722A1
公开(公告)日：2012-10-25
申请号：US13540801
申请日：2012-07-03
IPC分类号： H01L27/088
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
-
公开(公告)号：US20110309445A1
公开(公告)日：2011-12-22
申请号：US12816697
申请日：2010-06-16
CPC分类号： H01L29/66045 , H01L21/26506 , H01L21/84 , H01L27/105 , H01L27/1203 , H01L29/6656 , H01L29/66628 , H01L29/66659
摘要： Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.
摘要翻译： 本发明的实施例提供了制造具有类似物理尺寸但由于不同有效通道长度而具有不同操作特性的装置的能力。 通过在栅极和至少一个源极或漏极的边界处形成突变结点来控制有效沟道长度。 突变结在退火过程中影响扩散，这又控制有效沟道长度，允许同一芯片上物理上相似的器件具有不同的工作特性。
-
-
-
-
-
-
-
-
-
搜索结果
277 条记录 (耗时 0.029 秒)
