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71.发明授权Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference 失效具有包括在第一频率工作的振荡器的串行器的接口和包括以第二频率工作的振荡器的解串器等于半第一频率以最小化频率干扰
公开(公告)号：US5490282A
公开(公告)日：1996-02-06
申请号：US988593
申请日：1992-12-08
申请人： Daniel M. Dreps , Raymond P. Rizzo
发明人： Daniel M. Dreps , Raymond P. Rizzo
CPC分类号： H03M9/00
摘要： A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer.The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.
摘要翻译： 提供用于发送和接收串行数据的串行通信接口，包括串行器和解串器。 串行器被设计成使得串行器VCO的中心频率是解串器VCO的中心频率的一半。 串行器使用时钟的两边来混合串行位。 解串器设计不变。 两个VCO在独立的芯片上实现，两个芯片位于相同的金属化陶瓷基板上，其间距约为40毫米。 近频互动显着减少。
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公开(公告)号：US09473333B2
公开(公告)日：2016-10-18
申请号：US12028953
申请日：2008-02-11
CPC分类号： H04L25/03866
摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.
摘要翻译： 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。
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73.发明授权公开(公告)号：US09411750B2
公开(公告)日：2016-08-09
申请号：US13561446
申请日：2012-07-30
CPC分类号： G06F15/17318 , G06F9/00 , G06F11/3058 , G06F13/00 , G06F13/1673 , G06F13/24 , G06F13/4217 , G06F13/4282 , G06F15/803 , G06F19/00 , H04B1/38 , H04L12/56 , Y02D10/14 , Y02D10/151
摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
摘要翻译： 可校准通信链路包括多条平行线。 由自动机制确定的动态变量和/或可中断间隔进行校准。 校准优选地响应于由可执行软件过程产生的命令来启动，该指令响应于可能的即将发生的需求的检测而启动校准，如由温度变化，校准参数漂移，错误率等指示的。也优选地根据 可能的最小的设备功能中断，如低活动水平所示。 此外，在一个方面，可以临时暂停校准以发送数据，然后恢复。
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74.发明授权公开(公告)号：US08619432B2
公开(公告)日：2013-12-31
申请号：US12895251
申请日：2010-09-30
IPC分类号： H01R9/00
CPC分类号： H05K3/4623 , H05K1/0216 , H05K1/141 , H05K3/368 , H05K2201/10189 , Y10T29/49126 , Y10T29/49162 , Y10T29/53004
摘要： Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.
摘要翻译： 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。
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75.发明授权公开(公告)号：US08332552B2
公开(公告)日：2012-12-11
申请号：US12270569
申请日：2008-11-13
IPC分类号： G06F3/00 , G06F13/12 , G06F13/00 , G06F13/42 , G06F15/76 , G06F9/44 , H04L12/28 , H04L12/50 , H03K19/173 , H01L25/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。
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公开(公告)号：US07795762B2
公开(公告)日：2010-09-14
申请号：US11832379
申请日：2007-08-01
IPC分类号： H03K17/82
CPC分类号： H02H9/046
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.
摘要翻译： 片上电源噪声传感器检测电源电压的高频超频和欠压。 通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。 通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。 这具有以不需要校准的方式直接感测电源噪声的优点。 此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。 最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。
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公开(公告)号：US20090034144A1
公开(公告)日：2009-02-05
申请号：US11832379
申请日：2007-08-01
IPC分类号： H02H9/06
CPC分类号： H02H9/046
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise cars be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a matter that does not require calibration. Also, since the sensor requires only one power supply, it can he used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can he timed to detect down to whatever frequency is needed.
摘要翻译： 片上电源噪声传感器检测电源电压的高频超频和欠压。 通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。 通过比较这些电流，将检测非常高频率的电源噪声汽车的大小，并将其用于设置锁存器或添加到数字计数器。 这具有直接感测不需要校准的物质中的电源噪声的优点。 此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。 最后，它滤除电路设计人员不感兴趣的任何低频噪声，并且可以定时检测到任何需要的频率。
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公开(公告)号：US20080189457A1
公开(公告)日：2008-08-07
申请号：US12102036
申请日：2008-04-14
CPC分类号： G06F13/1694
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structures include a multimodal memory controller comprising: a transceiver circuit having at least one internal signal line, a first external signal line, a second external signal line, and a mode control signal line, the mode control signal line having asserted upon it a mode control signal, and the transceiver circuit configured to operate the external signal lines for single-ended signaling at a first voltage when the mode control signal is a first value and to operate the external signal lines for differential signaling at a second voltage when the mode control signal is a second value.
摘要翻译： 提供体现在机器可读介质中的设计结构。 设计结构的实施例包括多模式存储器控制器，包括：具有至少一个内部信号线，第一外部信号线，第二外部信号线和模式控制信号线的收发器电路，模式控制信号线已被断言 模式控制信号，并且收发器电路经配置以在模式控制信号为第一值时以第一电压操作用于单端信号的外部信号线，并且在第二电压下操作用于差分信号的外部信号线， 模式控制信号是第二值。
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79.发明授权公开(公告)号：US07212035B2
公开(公告)日：2007-05-01
申请号：US11055834
申请日：2005-02-11
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005
摘要： A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.
摘要翻译： 用于片外通信的线路驱动器包括多个并行级，每个并行级具有单独的输入。 当将线路驱动器输出节点驱动到逻辑0或逻辑1时，并联级各自具有受控阻抗。 线路驱动器控制器用于基于输出节点是在逻辑状态之间转换还是保持静态来选择驱动器级的组合来驱动输出节点。 在上电期间，测试程序尝试针对特定符号模式的驱动器级的不同组合，并确定动态和静态情况下线驱动器电阻之间的最佳比例是多少，并存储最佳组合。 馈送线路驱动器的数据流被实时采样以确定转换状态，并为每种情况选择最佳数量的驱动级。
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公开(公告)号：US20050253622A1
公开(公告)日：2005-11-17
申请号：US10845568
申请日：2004-05-13
申请人： Daniel M. Dreps , Anand Haridass , Bao Truong
发明人： Daniel M. Dreps , Anand Haridass , Bao Truong
CPC分类号： H04L25/061 , H04L25/45
摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.
摘要翻译： 两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。 产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。 导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。
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