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    Fiber optic amplifier with active elements feedback circuit
    1.
    发明授权
    Fiber optic amplifier with active elements feedback circuit 失效
    具有有源元件反馈电路的光纤放大器

    公开(公告)号：US5295161A

    公开(公告)日：1994-03-15

    申请号：US698626

    申请日：1991-05-10

    申请人： Daniel M. Dreps ,  Raymond P. Rizzo

    发明人： Daniel M. Dreps ,  Raymond P. Rizzo

    IPC分类号： H03F3/34 ,  H03F3/08 ,  H03F3/45 ,  H04B10/158 ,  H04L25/06

    CPC分类号： H04B10/6933 ,  H03F3/08

    摘要： A differential transimpedance amplifier used in amplifying optical signals transmitted with a balanced code has a level restore circuit which integrates the digital output of the amplifier and feeds back the result to one of the differential inputs of the amplifier. The feedback signal removes imbalances from the amplifier output. The balanced amplifier output can then be processed by a clock reconstruction circuit to accurately sample the received optical signal with a low bit error rate.

    摘要翻译： 用于放大用平衡码发射的光信号的差分跨阻放大器具有电平恢复电路，其对放大器的数字输出进行积分并将结果反馈到放大器的差分输入之一。 反馈信号消除了放大器输出的不平衡。 然后，平衡放大器输出可以由时钟重构电路处理，以以低误码率对接收的光信号进行精确采样。

    Electronic gain cell
    2.
    发明授权
    Electronic gain cell 失效
    电子增益电池

    公开(公告)号：US5039952A

    公开(公告)日：1991-08-13

    申请号：US512304

    申请日：1990-04-20

    申请人： Daniel M. Dreps ,  Raymond P. Rizzo

    发明人： Daniel M. Dreps ,  Raymond P. Rizzo

    IPC分类号： H03F3/08 ,  H03F3/45 ,  H03G1/00 ,  H03G3/20 ,  H04B10/00

    CPC分类号： H03G3/3084 ,  H03G1/0023

    摘要： An amplifier circuit comprises first and second gain cells connected in cascade. Each of the gain cells comprises first and second common emitter differential transistors, a current source coupled to the emitters of the transistors, a first plurality of forward biased, series diodes connected between a power supply terminal and a base of the first transistor, and a second plurality of forward biased, series diodes connected between the power supply terminal and a base of the second transistor. A collector of the first transistor of the first gain cell is connected to the base of the first transistor of the second gain cell, and a collector of the second transistor of a first gain cell is connected to the base of the second transistor of the second gain cell. Because of the low inherent resistance of the biasing diodes, the operating speed of the amplifier is large, and the current amplification can be large without exceeding the power supply voltage. The current source limits the gain for high level signals without causing saturation of the transistors and therefore, does not comprise operating speed. The gain of each cell equals the numbers of diodes connected to the base of the transistor until the level of the current source.

    Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference
    3.
    发明授权
    Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference 失效
    具有包括在第一频率工作的振荡器的串行器的接口和包括以第二频率工作的振荡器的解串器等于半第一频率以最小化频率干扰

    公开(公告)号：US5490282A

    公开(公告)日：1996-02-06

    申请号：US988593

    申请日：1992-12-08

    申请人： Daniel M. Dreps ,  Raymond P. Rizzo

    发明人： Daniel M. Dreps ,  Raymond P. Rizzo

    IPC分类号： H03M9/00 ,  G06F15/02

    CPC分类号： H03M9/00

    摘要： A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer.The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.

    摘要翻译： 提供用于发送和接收串行数据的串行通信接口，包括串行器和解串器。 串行器被设计成使得串行器VCO的中心频率是解串器VCO的中心频率的一半。 串行器使用时钟的两边来混合串行位。 解串器设计不变。 两个VCO在独立的芯片上实现，两个芯片位于相同的金属化陶瓷基板上，其间距约为40毫米。 近频互动显着减少。

    On-chip voltage controlled oscillator
    4.
    发明授权
    On-chip voltage controlled oscillator 失效
    片上压控振荡器

    公开(公告)号：US5604466A

    公开(公告)日：1997-02-18

    申请号：US345280

    申请日：1994-11-28

    申请人： Daniel M. Dreps ,  Raymond P. Rizzo

    发明人： Daniel M. Dreps ,  Raymond P. Rizzo

    IPC分类号： H03K3/282 ,  H03L7/099 ,  H03L7/14 ,  H03K3/281

    CPC分类号： H03K3/2821 ,  H03L7/099 ,  H03L7/14 ,  Y10S323/907

    摘要： An on-chip voltage controlled oscillator for use in an analog phase locked loop receives power from a voltage regulator which greatly reduces the noise seen by the voltage controlled oscillator. The voltage controlled oscillator has a DC bias section which supplies a relatively constant current to the multivibrator to assure a minimum operating frequency. A control signal is used to provide additional current which increases the speed of oscillation. The bias current reduces the transfer characteristics (MHz/volt) of the voltage controlled oscillator making it more immune to noise in the control signal.

    摘要翻译： 用于模拟锁相环的片上压控振荡器从电压调节器接收电力，这大大降低了压控振荡器所看到的噪声。 压控振荡器具有DC偏压部分，其向多谐振荡器提供相对恒定的电流以确保最小工作频率。 控制信号用于提供增加振荡速度的附加电流。 偏置电流降低了压控振荡器的传输特性（MHz /伏特），使其更加免于控制信号中的噪声。

    Digital phase detector with zero phase offset
    5.
    发明授权
    Digital phase detector with zero phase offset 失效

    公开(公告)号：US08718216B2

    公开(公告)日：2014-05-06

    申请号：US13242053

    申请日：2011-09-23

    申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0037 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/089

    摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

    Controllable voltage reference driver for a memory system
    7.
    发明授权
    Controllable voltage reference driver for a memory system 失效
    用于存储系统的可控参考电压驱动器

    公开(公告)号：US08089813B2

    公开(公告)日：2012-01-03

    申请号：US12175555

    申请日：2008-07-18

    申请人： Daniel M. Dreps

    发明人： Daniel M. Dreps

    IPC分类号： G11C16/06

    CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C5/063 ,  G11C5/147 ,  G11C8/08 ,  G11C29/021 ,  G11C29/028

    摘要： A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value.

    摘要翻译： 电压参考驱动器包括具有电压参考输出节点的分压器电路，以输出第一电压和第二电压之间的电压。 电压参考驱动器还包括耦合到处于第一电压的节点的第一可选择阻抗电路并进一步耦合到电压参考输出节点，以及第二可选阻抗电路，耦合到处于第二电压的节点，并且还耦合到电压基准 输出节点。 可选择第一可选择阻抗电路和第二可选择阻抗电路的组合，使得在阈值内的电压参考输出节点处保持恒定的阻抗。

    Multimodal memory controllers
    10.
    发明授权
    Multimodal memory controllers 失效
    多模式内存控制器

    公开(公告)号：US07773689B2

    公开(公告)日：2010-08-10

    申请号：US11670491

    申请日：2007-02-02

    申请人： Daniel M. Dreps ,  Dhaval R. Sejpal ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Dhaval R. Sejpal ,  Glen A. Wiedemeier

    IPC分类号： H04B3/00

    CPC分类号： G06F13/1694

    摘要： Multimodal memory controllers are disclosed that include: a transmitter having a first input signal line, a second input signal line, a first output signal line, a second output signal line, a first single-ended driver, a second single-ended driver, a differential transmitter, and a mode control signal line, the mode control signal line having asserted upon it a mode control signal, the transmitter configured to operate the output signal lines using the single-ended drivers at a first voltage when the mode control signal is a first value and to operate the output signal lines using the differential transmitter at a second voltage when the mode control signal is a second value, and the transmitter configured to protect the differential transmitter from the first voltage when the mode control signal is the first value.

    摘要翻译： 公开了多模式存储器控制器，其包括：具有第一输入信号线，第二输入信号线，第一输出信号线，第二输出信号线，第一单端驱动器，第二单端驱动器， 差分发射器和模式控制信号线，模式控制信号线已经向模式控制信号断言，所述发射机被配置为当模式控制信号为模拟控制信号时以第一电压使用单端驱动器来操作输出信号线 并且当所述模式控制信号是第二值时，使用所述差分发射机在所述第二电压下操作所述输出信号线，并且所述发射机被配置为当所述模式控制信号是所述第一值时保护所述差分发射机不受所述第一电压的影响。