-
公开(公告)号：US20250156296A1
公开(公告)日：2025-05-15
申请号：US18929369
申请日：2024-10-28
Applicant: Micron Technology, Inc.
Inventor： Luca Porzio , Nicola Colella , Rakeshkumar Dayabhai Vaghasiya , Deping He
Abstract: Methods, systems, and devices for memory allocation for a benchmark test are described. A memory system may be configured to allocate and deallocate portions of a volatile memory for specific uses based on detecting the occurrence of a benchmark testing operation. For example, the memory system may be configured to detect the occurrence of a benchmark testing operation based on the occurrence of one or more conditions. After detecting the benchmark testing operation, the memory system may deallocate a portion of the volatile memory associated with multiple-level cell accesses and may allocate (e.g., reallocate) the portion for storing additional logical-to-physical mappings.
-
公开(公告)号：US12293080B2
公开(公告)日：2025-05-06
申请号：US18233433
申请日：2023-08-14
Applicant: Micron Technology, Inc.
Inventor： Deping He , Caixia Yang
Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.
-
公开(公告)号：US20250123765A1
公开(公告)日：2025-04-17
申请号：US18830260
申请日：2024-09-10
Applicant: Micron Technology, Inc.
Inventor： Deping He , Bo Zhou , Caixia Yang
Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
-
公开(公告)号：US12111724B2
公开(公告)日：2024-10-08
申请号：US17648395
申请日：2022-01-19
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Jonathan S. Parry , Deping He , Xiangang Luo , Reshmi Basu
CPC classification number: G06F11/1068 , G06F11/1076
Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.
-
公开(公告)号：US20240312554A1
公开(公告)日：2024-09-19
申请号：US18600360
申请日：2024-03-08
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Deping He , Zhongyuan Lu
IPC: G11C29/52 , G11C11/406 , G11C29/02
CPC classification number: G11C29/52 , G11C11/40622 , G11C29/022
Abstract: Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.
-
Patent Agency Ranking
公开(公告)号：US20240311299A1
公开(公告)日：2024-09-19
申请号：US18672310
申请日：2024-05-23
Applicant: Micron Technology, Inc.
IPC: G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60
Abstract: A system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache. The processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. Detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. The processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.
-
公开(公告)号：US20240290411A1
公开(公告)日：2024-08-29
申请号：US18597454
申请日：2024-03-06
Applicant: Micron Technology, Inc.
Inventor： Chun S. Yeung , Deping He , Jonathan S. Parry
CPC classification number: G11C29/42 , G11C7/04 , G11C29/1201 , G11C29/4401 , G11C2029/1202 , G11C2029/1204
Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.
-
公开(公告)号：US20240281324A1
公开(公告)日：2024-08-22
申请号：US18443011
申请日：2024-02-15
Applicant: Micron Technology, Inc.
Inventor： Deping He , Caixia Yang
CPC classification number: G06F11/1064 , G06F11/076 , G06F11/1016
Abstract: Methods, systems, and devices for critical data management within a memory system are described. A memory system may avoid writing critical data to weak word lines. For example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. The memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. The memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.
-
公开(公告)号：US20240241665A1
公开(公告)日：2024-07-18
申请号：US18540448
申请日：2023-12-14
Applicant: Micron Technology, Inc.
Inventor： Deping He , Jonathan S. Parry
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and devices for partitioned transferring for write booster are described. Techniques are described for a memory system to transfer data from a buffer associated with a write booster mode to higher-density blocks of the memory system based on a type of the data stored in the buffer. A first type of data may be transferred from the buffer to the higher-density blocks before a second type of data may be transferred from the buffer to the higher-density blocks. Prioritizing the transfer of data from the buffer to the higher-density block based on the type of data may reduce a write amplification associated with the memory system.
-
公开(公告)号：US20240241663A1
公开(公告)日：2024-07-18
申请号：US18417808
申请日：2024-01-19
Applicant: Micron Technology, Inc.
Inventor： Caixia Yang , Deping He
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0676 , G06F3/0679
Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.
-
-
-
-
-
-
-
-
-
Search Results
128
records
(took 0.019 seconds)
