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    Dynamic power management network for memory devices
    71.
    发明授权
    Dynamic power management network for memory devices 有权

    公开(公告)号：US11029746B2

    公开(公告)日：2021-06-08

    申请号：US16427280

    申请日：2019-05-30

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan S. Parry

    IPC: G06F1/32 ,  G06F1/3234

    Abstract: Techniques for managing power usage in a memory subsystem are described. An operation type of each of a plurality of operations queued against one or more of a plurality of memory components is obtained. It is determined that at least two of the plurality of operations can be performed in parallel and that a first configuration of the plurality of memory components does not allow the at least two operations to be performed in parallel, the first configuration including a first set of power management cohorts. An interconnection of the plurality of memory components is reconfigured to change from the first configuration to a second configuration of the of the plurality of memory components, the second configuration including a second set of power management cohorts that allow the at least two operations to be performed in parallel.

    Methods for detecting and mitigating memory media degradation and memory devices employing the same
    73.
    发明授权
    Methods for detecting and mitigating memory media degradation and memory devices employing the same 有权

    公开(公告)号：US10475519B2

    公开(公告)日：2019-11-12

    申请号：US15933678

    申请日：2018-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan S. Parry ,  George B. Raad ,  James S. Rehmeyer ,  Timothy B. Cowles

    IPC: G11C7/00 ,  G11C16/34 ,  G11C11/406

    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

    REDUNDANT ARRAY MANAGEMENT TECHNIQUES
    75.
    发明申请
    REDUNDANT ARRAY MANAGEMENT TECHNIQUES 有权

    公开(公告)号：US20250086055A1

    公开(公告)日：2025-03-13

    申请号：US18890418

    申请日：2024-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

    IPC: G06F11/10

    Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

    COMPLETION FLAG FOR MEMORY OPERATIONS
    78.
    发明申请
    COMPLETION FLAG FOR MEMORY OPERATIONS 有权

    公开(公告)号：US20250004640A1

    公开(公告)日：2025-01-02

    申请号：US18759513

    申请日：2024-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan S. Parry

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

    IDENTIFICATION AND STORAGE OF BOOT INFORMATION AT A MEMORY SYSTEM
    79.
    发明申请
    IDENTIFICATION AND STORAGE OF BOOT INFORMATION AT A MEMORY SYSTEM 有权

    公开(公告)号：US20240402926A1

    公开(公告)日：2024-12-05

    申请号：US18678346

    申请日：2024-05-30

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Roberto Izzi ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Jonathan S. Parry ,  Reshmi Basu

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

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