公开(公告)号：US11437521B2

公开(公告)日：2022-09-06

申请号：US16596487

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/24

Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

公开(公告)号：US11329051B2

公开(公告)日：2022-05-10

申请号：US17005862

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe, III ,  Gurtej S. Sandhu ,  Armin Saeedi Vahdat ,  Si-Woo Lee ,  Scott E. Sills

IPC: H01L27/108 ,  G11C11/4097 ,  G11C8/14

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material. Selectively removing the sacrificial material in the first region to form first horizontal openings. Repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region. Depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.

公开(公告)号：US20220102356A1

公开(公告)日：2022-03-31

申请号：US17035819

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe III

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

公开(公告)号：US20220077149A1

公开(公告)日：2022-03-10

申请号：US17528128

申请日：2021-11-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L27/108

Abstract: A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.

公开(公告)号：US20220077000A1

公开(公告)日：2022-03-10

申请号：US17532856

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kurt D. Beigel

IPC: H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528 ,  H01L27/092 ,  H01L27/115 ,  H01L23/522 ,  H01L27/06

Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.

公开(公告)号：US20220068933A1

公开(公告)日：2022-03-03

申请号：US17005862

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe III ,  Gurtej S. Sandhu ,  Armin Saeedi Vahdat ,  Si-Woo Lee ,  Scott E. Sills

IPC: H01L27/108 ,  G11C8/14 ,  G11C11/4097

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material. Selectively removing the sacrificial material in the first region to form first horizontal openings. Repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region. Depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.

公开(公告)号：US11264377B2

公开(公告)日：2022-03-01

申请号：US17089374

申请日：2020-11-04

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/822 ,  H01L21/8238 ,  G11C29/44 ,  G11C5/02 ,  G11C29/14 ,  G11C29/12 ,  G11C7/10 ,  H01L29/66 ,  H01L27/105 ,  G11C29/00 ,  G11C29/42 ,  G11C7/12 ,  G11C5/14 ,  H03K19/20 ,  H03K19/0948 ,  G11C8/10 ,  G11C8/08

Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.

公开(公告)号：US20220059693A1

公开(公告)日：2022-02-24

申请号：US16998877

申请日：2020-08-20

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yi Fang Lee ,  Jerome A. Imonigie ,  Scott E. Sills ,  Aaron Michael Lowe

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/24 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11211384B2

公开(公告)日：2021-12-28

申请号：US15852870

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/78

Abstract: A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.

公开(公告)号：US20210375992A1

公开(公告)日：2021-12-02

申请号：US17400526

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.