公开(公告)号：US5018135A

公开(公告)日：1991-05-21

申请号：US412475

申请日：1989-09-26

申请人： Yoshihiro Ashi ,  Tadayuki Kanno

发明人： Yoshihiro Ashi ,  Tadayuki Kanno

IPC分类号： H04J3/06 ,  H04J3/08

CPC分类号： H04J3/08 ,  H04J3/0685

摘要： The present invention relates to an add drop multiplexer related to the synchronous multiplexing method, and includes a pass-through line connecting unit, which is driven by a timing signal extracted from a signal received through a transmission line and effects branching and insertion of the line as well as connection of pass-through lines at multiplexed levels; an office line connecting unit having an office interface function for each of other devices in a same office; a first frame aligner connecting multiplex branched signals from the pass-through line connecting unit with the office line connecting unit; and a second frame aligner connecting multiplex inserted signals from the office line connecting unit with the pass-through line connecting unit. In this way, since the whole pass-through line connecting unit can be driven only with the timing signal extracted from the received signal from the transmission line and the frame aligner can be removed from the path of the signal through the pass-through lines, it is possible to reduce the signal delay in the pass-through lines within the add drop multiplexer.

摘要翻译： 本发明涉及一种与同步多路复用方法相关的分插复用器，并且包括一个直通线连接单元，该直通线连接单元由从通过传输线接收的信号中提取的定时信号驱动，并实现线路的分支和插入 以及多路复用级别的直通线路的连接; 具有用于同一办公室中的每个其他设备的办公室接口功能的办公室线路连接单元; 第一框架对准器，其将来自所述直通线连接单元的多路分支信号与所述办公室线路连接单元连接; 以及第二框架对准器，其将来自办公室线路连接单元的多路插入信号与直通线连接单元连接。 以这种方式，由于只能通过从传输线从接收信号中提取的定时信号来驱动整个直通线连接单元，并且可以通过直通线从信号的路径移除帧对准器， 可以减小加法分路复用器内的直通线路中的信号延迟。

公开(公告)号：US20120236866A1

公开(公告)日：2012-09-20

申请号：US13512480

申请日：2009-11-30

申请人： Hideki Endo ,  Taisuke Ueta ,  Yoshihiro Ashi ,  Norio Miyazaki

发明人： Hideki Endo ,  Taisuke Ueta ,  Yoshihiro Ashi ,  Norio Miyazaki

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L43/0811 ,  H04L45/20 ,  H04L45/50

摘要： Provided is a communication system which is provided with a plurality of communication devices and transfers a packet between the plurality of communication devices through a communication path. When a packet is looped back at any of the communication devices on the communication path to verify connectivity of the communication path, a first communication device of the plurality of communication devices stores, in a first region of header information of the packet, first information for designating the communication device at which the packet is looped back, further stores, in a second region of the header information of the packet, second information on a loopback point in the designated communication device at which the packet is looped back, and sends the packet to which the first information and the second information have been added.

摘要翻译： 提供了一种通信系统，其具有多个通信设备，并且通过通信路径在多个通信设备之间传送分组。 当分组环回在通信路径上的任何通信设备上以验证通信路径的连通性时，多个通信设备中的第一通信设备在分组的报头信息的第一区域中存储用于 指定分组环回的通信设备，还在分组的报头信息的第二区域中存储关于分组环回的指定通信设备中的回送点的第二信息，并发送分组 添加了第一个信息和第二个信息。

公开(公告)号：US07620074B2

公开(公告)日：2009-11-17

申请号：US11511301

申请日：2006-08-29

申请人： Takeshi Yasuda ,  Yoshihiro Ashi ,  Ken Mutou

发明人： Takeshi Yasuda ,  Yoshihiro Ashi ,  Ken Mutou

IPC分类号： H04J3/06

CPC分类号： H04J3/0664 ,  H04J3/0688 ,  H04J2203/0085 ,  H04L12/403

摘要： A communication system is provided which allows synchronous devices in different synchronous communication networks to have synchronous communications with one another via an asynchronous communication network. In the communication system of the present invention, a master communication device generates a master clock based on a reference clock which is provided by a clock supplier. The master communication device sends a synchronization information frame, which contains information about the generated master clock, to plural slave communication devices via the asynchronous communication network. The slave communication devices each reproduce the master clock from the received synchronization information frame.

摘要翻译： 提供一种通信系统，其允许不同同步通信网络中的同步设备经由异步通信网络彼此进行同步通信。 在本发明的通信系统中，主通信装置基于由时钟提供者提供的基准时钟生成主时钟。 主通信设备经由异步通信网络将包含有关生成的主时钟的信息的同步信息帧发送到多个从通信设备。 从属通信设备各自从接收到的同步信息帧中再现主时钟。

公开(公告)号：US6005699A

公开(公告)日：1999-12-21

申请号：US927277

申请日：1997-09-11

申请人： Keiji Tomooka ,  Naohiro Sakakida ,  Shin Nishimura ,  Yoshihiro Ashi ,  Hironari Matsuda ,  Satoshi Aoki ,  Yukio Nakano ,  Masahiro Takatori ,  Toru Kazawa ,  Shinya Sasaki ,  Ryoji Takeyari ,  Hiroyuki Nakano

发明人： Keiji Tomooka ,  Naohiro Sakakida ,  Shin Nishimura ,  Yoshihiro Ashi ,  Hironari Matsuda ,  Satoshi Aoki ,  Yukio Nakano ,  Masahiro Takatori ,  Toru Kazawa ,  Shinya Sasaki ,  Ryoji Takeyari ,  Hiroyuki Nakano

IPC分类号： H04B10/17 ,  H04J14/02 ,  H04Q11/00 ,  H04Q11/04 ,  H04B10/20

CPC分类号： H04J14/0295 ,  H04B10/2939 ,  H04J14/02 ,  H04J14/0241 ,  H04Q11/0062 ,  H04Q11/0478 ,  H04J14/0226 ,  H04J14/0227 ,  H04J14/0279 ,  H04J14/0283 ,  H04J14/0284 ,  H04J14/0286 ,  H04J14/0294 ,  H04J2203/0051 ,  H04Q2011/0069 ,  H04Q2011/0081 ,  H04Q2011/0083

摘要： An optical transmission system accomplishes optical transmission to a long distance by combining a multiplexing line terminal with optical amplifiers, linear repeaters, and regenerators with optical amplifiers combined together. The system also accomplishes the optical transmission to a short distance by directly connecting the linear terminals therebetween, with an electric-to-optic converter replaced by an electric-to-optic converter having a semiconductor amplifier, with an optic-to-electric converter by an optic-to-electric converter having an avalanche photodiode as light receiver, an with no use of any optical booster amplifier and optical preamplifier in the multiplexing line terminal. With these, the optical transmission system can be easily constructed depending on the transmission distance required.

摘要翻译： 光传输系统通过将多路复用线路终端与光放大器，线性中继器和具有组合在一起的光放大器的再生器组合来实现长距离的光传输。 该系统还通过直接连接它们之间的线性端子来实现光传输到短距离，其中电光转换器由具有半导体放大器的电光转换器代替，其中光电转换器由 具有雪崩光电二极管作为光接收器的光电转换器，在复用线路终端中不使用任何光学增强放大器和光学前置放大器。 利用这些，可以根据所需的传输距离容易地构造光传输系统。

公开(公告)号：US5896387A

公开(公告)日：1999-04-20

申请号：US789116

申请日：1997-01-27

申请人： Hiroyuki Fujita ,  Naohisa Hamaguchi ,  Yoshihiro Ashi

发明人： Hiroyuki Fujita ,  Naohisa Hamaguchi ,  Yoshihiro Ashi

IPC分类号： H04J3/00 ,  H04J3/08 ,  H04J3/16 ,  H04J3/02

CPC分类号： H04J3/085 ,  H04J3/1611

摘要： A multiplex conversion unit is configured with the functions required for a specific network to which it is applicable more economically. Each OC-12IF circuit pack includes a switch for performing time slot assignment (TSA) between a plurality of high-speed transmission lines accommodated in the OC-12IF circuit pack and at least a low-speed transmission line accommodated in at least a DS3IF circuit pack. An ADM circuit pack includes a switch for performing time slot interchange (TSI) between the high-speed transmission lines and the low-speed transmission line. In an application to a network requiring the TSI function, the switch of the OC-12IF circuit pack performs only the add/drop multiplex (ADM) operation between the signals input/output by the high-speed transmission lines and the ADM circuit pack, and the switch on the ADM circuit pack performs the TSI operation. In an application not requiring the TSI, on the other hand, the TSA operation is performed by the switch of the OC-12IF circuit pack using a THRU circuit pack having a wiring connecting the OC-12IF circuit pack and a DS3IF circuit pack in place of the ADM circuit pack.

摘要翻译： 复用转换单元被配置为具有更经济可用的特定网络所需的功能。 每个OC-12IF电路板包括用于在容纳在OC-12IF电路板中的多个高速传输线之间执行时隙分配（TSA）的开关和至少一个容纳在至少DS3IF电路中的低速传输线 包。 ADM电路板包括用于在高速传输线和低速传输线之间执行时隙交换（TSI）的开关。 在需要TSI功能的网络的应用中，OC-12IF电路板的开关仅执行由高速传输线和ADM电路板输入/输出的信号之间的分插复用（ADM）操作， 并且ADM电路板上的开关执行TSI操作。 另一方面，在不需要TSI的应用中，通过使用具有连接OC-12IF电路板和DS3IF电路板的布线的THRU电路板来切换OC-12IF电路板来执行TSA操作 的ADM电路板。

公开(公告)号：US5634097A

公开(公告)日：1997-05-27

申请号：US027643

申请日：1993-03-08

申请人： Yoshihiro Ashi ,  Toshihiko Fujita ,  Hiromi Ueda ,  Haruhiko Matsunaga

发明人： Yoshihiro Ashi ,  Toshihiko Fujita ,  Hiromi Ueda ,  Haruhiko Matsunaga

IPC分类号： H04L12/70 ,  H04Q11/04 ,  G06F11/00 ,  H04L12/56

CPC分类号： H04Q11/0478 ,  H04L2012/5623 ,  H04L2012/5626

摘要： A method and apparatus of tracing VP's (virtual paths) wherein operational information of VP connectors are collected through OAM (operation and maintenance) cells. The VP connectors establish a connection at a VP level within a network in which the cells are transferred in an ATM (asynchronous transfer mode). Each VP connector detects an OAM cell for VP tracing as received from another of the VP connectors, and judges if an area for affixing the operational information in the VP connector itself exists in the detected OAM cell. In the VP connector when the area exists, the detected OAM cell is specified to be the OAM cell for writing the operational information thereinto, and the specified OAM cell is sent out after affixing the operational information thereto. When the area does not exit, the OAM cell received from the other VP connector is sent out after indicating therein that the received OAM cell is not the rearmost cell, the OAM cell for the VP tracing is generated anew, and the generated cell is sent out after indicating therein that the generated OAM cell is the rearmost cell. Also the operational information is affixed to newly generated OAM cell.

摘要翻译： 追踪VP（虚拟路径）的方法和装置，其中通过OAM（操作和维护）单元收集VP连接器的操作信息。 VP连接器在网络中的VP级建立连接，其中小区在ATM（异步传输模式）中传输。 每个VP连接器检测到从另一个VP连接器接收到的用于VP跟踪的OAM小区，并且判断在所检测的OAM小区中是否存在用于附加VP连接器中的操作信息的区域。 在存在该区域的VP连接器中，检测到的OAM单元被指定为用于写入其中的操作信息的OAM单元，并且在将操作信息附加到其上之后发送指定的OAM单元。 当该区域不退出时，从其他VP连接器接收的OAM小区在其中指示接收到的OAM小区不是最后一个小区之后被发出，用于VP跟踪的OAM小区重新生成，并且生成的小区被发送 在其中指示所生成的OAM信元是最后一个信元。 操作信息也附加到新生成的OAM单元。

公开(公告)号：US5600631A

公开(公告)日：1997-02-04

申请号：US356617

申请日：1994-12-15

申请人： Masahiro Takatori ,  Yoshihiro Ashi ,  Hiroyuki Fujita

发明人： Masahiro Takatori ,  Yoshihiro Ashi ,  Hiroyuki Fujita

IPC分类号： H04J3/00 ,  H04J3/08 ,  H04Q11/04 ,  H04J3/14

CPC分类号： H04Q11/0478 ,  H04J3/085 ,  H04J2203/0005 ,  H04J2203/0042 ,  H04J2203/0089

摘要： In order that the various ring-switching modes of 2-Fiber BLSR, 4-Fiber BLSR and UPSR may be switched merely by changing a software, space division switches are disposed across an add drop switch, and one output drop switch and one output of the second space division switch are connected with the input stage of a selector which can be selected at the unit of a time slot. As a result, the various ring-switching modes can be switched merely by changing the software while suppressing the scale of the switch. Moreover, the change from the ring switch to the linear switch and vice versa can be effected.

摘要翻译： 为了仅通过改变软件就可以切换2光纤BLSR，4光纤BLSR和UPSR的各种环路切换模式，空分开关设置在加法分支开关上，一个输出下拉开关和一个输出 第二空分开关与可以以时隙为单位选择的选择器的输入级连接。 结果，可以仅通过在抑制开关的规模的同时改变软件来切换各种环形切换模式。 此外，可以实现从环形开关到线性开关的变化，反之亦然。

公开(公告)号：US5331639A

公开(公告)日：1994-07-19

申请号：US609647

申请日：1990-11-06

申请人： Masahiro Takatori ,  Yukio Nakano ,  Keiichi Ishida ,  Takashi Mori ,  Yoshihiro Ashi ,  Tadayuki Kanno ,  Hiromi Ueda

发明人： Masahiro Takatori ,  Yukio Nakano ,  Keiichi Ishida ,  Takashi Mori ,  Yoshihiro Ashi ,  Tadayuki Kanno ,  Hiromi Ueda

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04L7/00 ,  H04Q11/04

CPC分类号： H04J3/0623 ,  H04J2203/0089

摘要： A method and an apparatus for converting a frame phase of a signal having a frame structure specified in the CCITT recommendations which contains N (N: an integer 2 or above) pieces of frames applied with time-division/multiplex, in which the N pieces of frames are given to N pieces of memories, respectively, a write address is given independently to each memory so that the N pieces of frames are written in the respective memories in a same phase as the phase in the signal, a read address is given independently to each memory so that the N pieces of frames are read out of the respective memories in a same phase as the write phase, a difference between a write address and a read address in each memory is set identical under an initial state, and justification is executed for a frame which is read out of the memory in accordance with a difference between existing write address and read address in each memory, whereby to perform frame phase conversion while maintaining relative phase among respective frames.

摘要翻译： 一种用于转换具有CCITT建议中指定的帧结构的信号的帧相位的方法和装置，其包含以时分复用应用的N（N：整数2或以上）帧，其中N个 分别给予N个存储器，每个存储器独立地给出写入地址，使得N个帧以与信号中的相位相同的相位写入各个存储器中，给出读取地址 独立于每个存储器，使得N个帧在与写入相位相同的相位中从各个存储器读出，每个存储器中的写入地址和读取地址之间的差在初始状态下被设置为相同，并且对齐 根据存储器中的现有写入地址和读取地址之间的差异从存储器中读出的帧被执行，由此执行帧相位转换，同时保持相对相位 g各个框架。

公开(公告)号：US5321688A

公开(公告)日：1994-06-14

申请号：US791504

申请日：1991-11-14

申请人： Yukio Nakano ,  Yoshihiro Ashi

发明人： Yukio Nakano ,  Yoshihiro Ashi

IPC分类号： H04L29/14 ,  H04L1/00 ,  H04L12/70 ,  H04Q11/04 ,  H04L1/24

CPC分类号： H04L1/0083 ,  H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/5627

摘要： A method for transmitting virtual path failure information in an asynchronous transfer mode network the method includes performing search against a table storing virtual paths being used for generating failure indicative cells for respective ones of the virtual paths when failure of a transmission line is detected. The generated failure indicative cells are transmitted to all of the other apparatuses connected in downstream signal transmitting directions through the virtual path sequentially for a number of predetermined times, and subsequently, intermittently with an interval of a given period of time. When failure is removed, a normal cell is immediately transmitted.

摘要翻译： 一种用于在异步传输模式网络中发送虚拟路径故障信息的方法，该方法包括当检测到传输线路故障时，针对存储虚拟路径的表执行搜索，所述虚拟路径用于在虚拟路径中的相应虚拟路径生成故障指示小区。 所生成的故障指示单元通过虚拟路径顺序地传送到连续在下游信号发送方向上的所有其他设备数个预定时间，并且随后以给定时间间隔间歇地发送。 当故障被去除时，正常的单元被立即传送。

公开(公告)号：US5038351A

公开(公告)日：1991-08-06

申请号：US339813

申请日：1989-04-18

申请人： Kazutaka Sakai ,  Yoshihiro Ashi

发明人： Kazutaka Sakai ,  Yoshihiro Ashi

IPC分类号： H03M5/06 ,  H03M5/14 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L7/08 ,  H04L25/49

CPC分类号： H04L7/04 ,  H03M5/145 ,  H04L7/0337

摘要： A CMI block synchronization circuit includes a clock deriving circuit, CMI decoding circuit, signal selection determining circuit and a selection circuit. In the clock deriving circuit, a clock CLK.sub.o having the same phase as a binary signal and a clock CLK.sub..pi. having a phase which is different 180.degree. from the clock CLK.sub.o are derived from an inputted CMI code signal. In the CMI decoding circuit, the inputted CMI code signal is decoded by using the clocks derived and violating bits are detected. In the signal selection determining circuit, the clocks CLK.sub.o and CLK.sub..pi. are counted respectively. Only when one of the count values is equal to or higher than a setting value and another count value is lower than another setting value is it regarded that a block asynchronization is caused in decoding the CMI code signal. In this case, the decoded output being selected until that time is changed over to another decoded output, whereby the block synchronization is retained even during burst errors.

摘要翻译： CMI块同步电路包括时钟导出电路，CMI解码电路，信号选择确定电路和选择电路。 在时钟导出电路中，从输入的CMI码信号导出与二进制信号具有相同相位的时钟CLKo和具有与时钟CLKo不同180°的相位的时钟CLK pi。 在CMI解码电路中，通过使用导出的时钟对所输入的CMI码信号进行解码，检测出违反位。 在信号选择确定电路中，分别计数时钟CLKo和CLK pi。 只有当其中一个计数值等于或高于设定值，另一个计数值低于另一设定值时，认为在对CMI代码信号进行解码时引起块异步。 在这种情况下，选择直到那个时间的解码输出被转换到另一解码输出，由此即使在突发错误期间也保持块同步。