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公开(公告)号：US20210020218A1
公开(公告)日：2021-01-21
申请号：US16514431
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra
IPC: G11C11/16
Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US20210004174A1
公开(公告)日：2021-01-07
申请号：US16503015
申请日：2019-07-03
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Innocenzo Tortorelli
Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.
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公开(公告)号：US10854674B2
公开(公告)日：2020-12-01
申请号：US15693102
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US20200303462A1
公开(公告)日：2020-09-24
申请号：US16892459
申请日：2020-06-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20200258943A1
公开(公告)日：2020-08-13
申请号：US16863555
申请日：2020-04-30
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.
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Patent Agency Ranking
公开(公告)号：US10559353B2
公开(公告)日：2020-02-11
申请号：US16001790
申请日：2018-06-06
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.
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公开(公告)号：US20190123105A1
公开(公告)日：2019-04-25
申请号：US16216100
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20190067371A1
公开(公告)日：2019-02-28
申请号：US15689155
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Innocenzo Tortorelli
IPC: H01L27/24 , H01L45/00 , H01L27/115
Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
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公开(公告)号：US20190065077A1
公开(公告)日：2019-02-28
申请号：US15683821
申请日：2017-08-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.
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公开(公告)号：US20180374897A1
公开(公告)日：2018-12-27
申请号：US16118632
申请日：2018-08-31
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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