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    LOGICAL OPERATIONS USING MEMORY CELLS
    72.
    发明申请
    LOGICAL OPERATIONS USING MEMORY CELLS 审中-公开

    公开(公告)号：US20200234755A1

    公开(公告)日：2020-07-23

    申请号：US16840874

    申请日：2020-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Glen E. Hush

    IPC: G11C11/4091 ,  G11C11/4097 ,  H03K19/20 ,  H03K19/0948 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

    Apparatuses and methods for performing logical operations using sensing circuitry
    73.
    发明授权
    Apparatuses and methods for performing logical operations using sensing circuitry 有权

    公开(公告)号：US10535384B2

    公开(公告)日：2020-01-14

    申请号：US16253750

    申请日：2019-01-22

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning

    IPC: G11C16/04 ,  H03K19/00 ,  G11C7/22 ,  G06F12/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G06F3/06 ,  G06F7/523 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

    APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE STRUCTURES
    76.
    发明申请
    APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE STRUCTURES 审中-公开

    公开(公告)号：US20190286337A1

    公开(公告)日：2019-09-19

    申请号：US16433803

    申请日：2019-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

    IPC: G06F3/06 ,  G11C7/10 ,  G06F15/78 ,  G11C29/28 ,  G11C8/12

    Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.

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