公开(公告)号：US11301383B2

公开(公告)日：2022-04-12

申请号：US16928999

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Cagdas Dirik ,  Laurent Isenegger ,  Robert M. Walker

IPC: G06F12/0806

Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.

公开(公告)号：US20220027095A1

公开(公告)日：2022-01-27

申请号：US17498415

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US20210109678A1

公开(公告)日：2021-04-15

申请号：US17127850

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US20200159434A1

公开(公告)日：2020-05-21

申请号：US16195018

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.

公开(公告)号：US20190121546A1

公开(公告)日：2019-04-25

申请号：US16103585

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US10157019B2

公开(公告)日：2018-12-18

申请号：US15906872

申请日：2018-02-27

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  James J. Shawver

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/10 ,  G11C11/4097

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

公开(公告)号：US20180336933A1

公开(公告)日：2018-11-22

申请号：US16047949

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C7/1006

Abstract: The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.

公开(公告)号：US20180329648A1

公开(公告)日：2018-11-15

申请号：US16043959

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  James J. Shawver

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4097

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

公开(公告)号：US20180188996A1

公开(公告)日：2018-07-05

申请号：US15906872

申请日：2018-02-27

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  James J. Shawver

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4097

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

公开(公告)号：US20180039484A1

公开(公告)日：2018-02-08

申请号：US15227459

申请日：2016-08-03

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jesse F. Lovitt ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F7/58 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G06F7/588 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.