公开(公告)号：US20150205589A1

公开(公告)日：2015-07-23

申请号：US14161617

申请日：2014-01-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G06F9/45

CPC classification number: G06F8/4432 ,  Y02D10/41

Abstract: A system, method, and computer program product are provided for compiling a computer program comprising arithmetic operations having different requirements with respect to numeric dynamic range, numeric resolution, or any combination thereof. The method comprises generating a transformed graph representation of the computer program by applying propagation rules that provide for relaxed numeric requirements, where applicable, and generating output code based on the transformed graph representation. Relaxing numeric requirements, such as dynamic range and resolution requirements, may advantageously lower power consumption during execution of the computer program.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于编译包括关于数字动态范围，数字分辨率或其任何组合具有不同要求的算术运算的计算机程序。 该方法包括通过应用传播规则来生成计算机程序的变换图表示，该传播规则在适用的情况下提供放松的数字要求，并且基于变换的图表示产生输出代码。 轻松的数字要求（例如动态范围和分辨率要求）可有利地降低计算机程序执行期间的功耗。

公开(公告)号：US20140269011A1

公开(公告)日：2014-09-18

申请号：US13933058

申请日：2013-07-01

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: G11C11/4096

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069

Abstract: A system includes a control circuit and first, second, and third ground-referenced single-ended signaling (GRS) driver circuits that are each coupled to an output signal. The control circuit is configured to generate a first, second, and third set of control signals that are each based on a respective phase of a clock signal. Each GRS driver circuit is configured to pre-charge a capacitor to store a charge based on the respective set of control signals during at least one phase of the clock signal and drive the output signal relative to a ground network by discharging the charge during a respective phase of the clock signal.

Abstract translation: 系统包括控制电路和分别耦合到输出信号的第一，第二和第三接地参考单端信令（GRS）驱动器电路。 控制电路被配置为产生基于时钟信号的相应相位的第一，第二和第三组控制信号。 每个GRS驱动器电路被配置为在时钟信号的至少一个相位期间基于相应的控制信号集来预先充电电容器以存储电荷，并且在相应的时间期间通过放电来驱动输出信号相对于地面网络 时钟信号的相位。

公开(公告)号：US20140266417A1

公开(公告)日：2014-09-18

申请号：US13973947

申请日：2013-08-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: H01L23/535

CPC classification number: H01L23/535 ,  G06F13/00 ,  G06F13/4072 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H03K19/00 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，图形处理集群（GPC）芯片和被配置为包括第一处理器芯片，GPC芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 GPC芯片被配置为包括第二单端信令接口电路并执行着色器程序。 在MCM封装内制造的第二组电迹线，用于将第二单端信令接口电路耦合到互连电路。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

公开(公告)号：US20140139275A1

公开(公告)日：2014-05-22

申请号：US13681929

申请日：2012-11-20

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally ,  Stephen G. Tell

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03K5/135

Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.

Abstract translation: 提供了用于变形容限同步的方法和系统。 接收表示相对于第一时钟信号的第二时钟信号的相位和表示第二时钟信号和第一时钟信号之间的相对周期的周期值的相位值。 基于相位值和周期值计算第二时钟信号相对于与第一时钟信号的下一个转换相对应的第一时钟信号的外推相位值。

公开(公告)号：US08604855B2

公开(公告)日：2013-12-10

申请号：US13921138

申请日：2013-06-18

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Ge Yang

IPC: H03K3/356

CPC classification number: H03K3/36 ,  H03K3/012 ,  H03K3/356121

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。

公开(公告)号：US10997496B2

公开(公告)日：2021-05-04

申请号：US15458837

申请日：2017-03-14

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G06F7/523 ,  G06N3/08

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by the processing element to produce destination addresses for each result value in the plurality of result values. Each result value is transmitted to a destination accumulator associated with the destination address for the result value.

公开(公告)号：US20210089864A1

公开(公告)日：2021-03-25

申请号：US17111875

申请日：2020-12-04

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/04 ,  G06F17/11 ,  G06F9/30 ,  G06F9/38 ,  G06N3/08 ,  G06N3/063

Abstract: A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.

公开(公告)号：US20180046906A1

公开(公告)日：2018-02-15

申请号：US15458799

申请日：2017-03-14

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/063 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/4824 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/082 ,  G06N3/084

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. A first vector comprising only non-zero weight values and first associated positions of the non-zero weight values within a 3D space is received. A second vector comprising only non-zero input activation values and second associated positions of the non-zero input activation values within a 2D space is received. The non-zero weight values are multiplied with the non-zero input activation values, within a multiplier array, to produce a third vector of products. The first associated positions are combined with the second associated positions to produce a fourth vector of positions, where each position in the fourth vector is associated with a respective product in the third vector. The products in the third vector are transmitted to adders in an accumulator array, based on the position associated with each one of the products.

公开(公告)号：US09804621B2

公开(公告)日：2017-10-31

申请号：US13759964

申请日：2013-02-05

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G05F1/618 ,  H02M1/00 ,  G06F1/26 ,  H02M3/158

CPC classification number: G05F1/618 ,  G06F1/26 ,  H02M1/00 ,  H02M3/158 ,  H02M3/1582 ,  H02M3/1584

Abstract: A system and method are provided for generating non-overlapping enable signals. A peak voltage level is measured at an output of a current source that is configured to provide current to a voltage control mechanism. The non-overlapping enable signals are generated for the voltage control mechanism based on the peak voltage level. A system includes the current source, a downstream controller, and the voltage control mechanism that is coupled to the load. The current source is configured to provide current to the voltage control mechanism. The controller is configured to measure the peak voltage level at the output of the current source and generate the non-overlapping enable signals based on the peak voltage level. The non-overlapping enable signals provide a portion of the current to the load.

公开(公告)号：US09800158B2

公开(公告)日：2017-10-24

申请号：US13754791

申请日：2013-01-30

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G05F1/24 ,  H02M3/158 ,  H02M3/156 ,  H02M3/155

CPC classification number: H02M3/1582 ,  H02M3/155 ,  H02M3/156 ,  H02M3/158 ,  H02M3/1584

Abstract: A system and method are provided for regulating a voltage level at a load. A current source generates a current and a voltage control mechanism provides a portion of the current to regulate the voltage level at the load. When the voltage level at the load is greater than a maximum voltage level, the current source is decoupled from the load and the current source is coupled to a current sink to reduce the voltage level at the load. An electric power conversion comprises the current source and the voltage control mechanism. A downstream controller is configured to control the voltage control mechanism to decouple the current source from the load and couple the current source to a current sink to reduce the voltage level at the load when the voltage level at the load is greater than a maximum voltage level.