公开(公告)号：US08901566B2

公开(公告)日：2014-12-02

申请号：US11848268

申请日：2007-08-31

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L29/00 ,  H01L27/118 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：US20120196412A1

公开(公告)日：2012-08-02

申请号：US13446609

申请日：2012-04-13

申请人： Huajie CHEN ,  Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Huajie CHEN ,  Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：US07994612B2

公开(公告)日：2011-08-09

申请号：US12106476

申请日：2008-04-21

申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

IPC分类号： H01L21/02

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/785

摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。

公开(公告)号：US07754569B2

公开(公告)日：2010-07-13

申请号：US11928583

申请日：2007-10-30

申请人： Omer H. Dokumaci ,  Oleg Gluschenkev

发明人： Omer H. Dokumaci ,  Oleg Gluschenkev

IPC分类号： H01L21/336

CPC分类号： H01L29/105 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/6659 ,  H01L29/66636

摘要： An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.

摘要翻译： 提供了一种用于根据栅极长度控制半导体器件的有源区域中的净掺杂的装置和方法。 选择补偿掺杂剂是一种掺杂剂，其将电中和衬底中相反类型的掺杂剂。 通过以相对高的角度和高能量注入补偿掺杂剂，补偿掺杂剂将进入并通过用于短通道的栅极区域，并且对栅极区域内的总掺杂剂浓度几乎没有或没有影响。 在通道长度较长的情况下，高注入角度和高注入能量使得补偿掺杂剂落入通道内，从而中和相反类型的掺杂剂的一部分。

公开(公告)号：US07745277B2

公开(公告)日：2010-06-29

申请号：US11065061

申请日：2005-02-25

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/7849

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成半导体层。 衬底的第一区域被膨胀以向上推动半导体层的第一部分，从而对第一部分施加拉伸应力。 衬底的第二区域被压缩以拉下半导体层的第二部分，从而向第二部分施加压应力。 在半导体层的第一部分上形成N型器件，并且在半导体层的第二部分上形成P型器件。

公开(公告)号：US07595247B2

公开(公告)日：2009-09-29

申请号：US11753862

申请日：2007-05-25

申请人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

摘要翻译： 通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。 然后形成偏移，然后执行延伸注入工艺。 这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。 与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。 另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

公开(公告)号：US20080290409A1

公开(公告)日：2008-11-27

申请号：US11753862

申请日：2007-05-25

申请人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

摘要翻译： 通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。 然后形成偏移，然后执行延伸注入工艺。 这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。 与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。 另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

公开(公告)号：US20080230840A1

公开(公告)日：2008-09-25

申请号：US12132705

申请日：2008-06-04

申请人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

发明人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

IPC分类号： H01L49/00

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

公开(公告)号：US07402870B2

公开(公告)日：2008-07-22

申请号：US10711899

申请日：2004-10-12

申请人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

发明人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

IPC分类号： H01L29/76

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US20080128861A1

公开(公告)日：2008-06-05

申请号：US11555906

申请日：2006-11-02

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L29/73

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。