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公开(公告)号：US20090261425A1
公开(公告)日：2009-10-22
申请号：US12106476
申请日：2008-04-21
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。
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公开(公告)号：US07994612B2
公开(公告)日：2011-08-09
申请号：US12106476
申请日：2008-04-21
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。
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3.发明申请DEVICE STRUCTURES INCLUDING DUAL-DEPTH TRENCH ISOLATION REGIONS AND DESIGN STRUCTURES FOR A STATIC RANDOM ACCESS MEMORY 审中-公开设备结构包括双深度分离隔离区域和静态随机访问存储器的设计结构公开(公告)号：US20090267156A1
公开(公告)日：2009-10-29
申请号：US12111285
申请日：2008-04-29
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L21/823481 , H01L27/1104
摘要： Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second pluralities of doped regions of a second conductivity type in the first device region. A shallow trench isolation region extends laterally across in the device region to connect the first and second deep trench isolation regions, and is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends from the top surface into the semiconductor layer to a first depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要翻译： 静态随机存取存储器的器件结构和设计结构。 器件结构包括在半导体层中的第一导电类型的阱，半导体层中的横向地限定阱中的器件区域的第一和第二深沟槽隔离区以及第二和第二多个第二导电类型的掺杂区 在第一个设备区域。 浅沟槽隔离区域在器件区域中横向延伸以连接第一和第二深沟槽隔离区域，并且设置在第一和第二多个掺杂区域之间的器件区域中。 浅沟槽隔离区域从顶表面延伸到半导体层到第一深度，使得阱在浅沟槽隔离区域下连续。 栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。
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4.发明授权公开(公告)号：US08536018B1
公开(公告)日：2013-09-17
申请号：US13467314
申请日：2012-05-09
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/108
CPC分类号： H01L21/76283 , H01L21/76232 , H01L21/84
摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.
摘要翻译： 提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。 一种方法包括在衬底上沉积多个层，并在多个层上形成层。 该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。 该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。 该方法还包括形成与深沟槽对准的浅沟槽。 该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。
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5.发明申请METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL 审中-公开制备记忆细胞的双深度分离分离区的方法公开(公告)号：US20090269897A1
公开(公告)日：2009-10-29
申请号：US12111266
申请日：2008-04-29
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823481 , H01L27/1104
摘要： Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要翻译： 用于制造用于存储单元的双深度沟槽隔离区域的方法。 在半导体层中形成第一和第二深沟槽隔离区域，该半导体层横向地限定半导体层中的第一导电类型的阱中的器件区域。 在器件区域中形成第二导电类型的第一和第二多个掺杂区域。 形成了浅沟槽隔离区域，其横跨穿过器件区域从第一深沟槽隔离区域延伸到第二深沟槽隔离区域。 浅沟槽隔离区设置在第一和第二多个掺杂区域之间的器件区域中。 浅沟槽隔离区域延伸到半导体层中的深度，使得阱在浅沟槽隔离区域之下是连续的。 栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。
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6.发明申请HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME 审中-公开高密度指针式CMOS反相器，以及其制造和布局公开(公告)号：US20110291193A1
公开(公告)日：2011-12-01
申请号：US12788362
申请日：2010-05-27
CPC分类号： H01L27/1203 , H01L21/26586 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.
摘要翻译： 形成在SOI衬底上的高密度，不对称对接结CMOS反相器可以包括：非对称p-FET，其仅在p-FET的源极侧包括卤素注入; 一个不对称的n-FET，其仅在n-FET的源极侧包括一个卤素注入; 以及包括所述SOI衬底的区域的对接结，其中所述非对称n-FET的漏极区域和所述非对称p-FET的漏极区域直接物理接触。 可以通过以离子吸收结构覆盖CMOS反相器的第一FET的顺序过程形成非对称晕环植入物，并且仅向第二FET的源极侧施加成角度的离子辐射，去除离子吸收结构，覆盖第一 FET，具有第二离子吸收结构，并且仅向第二FET的源极侧施加成角度的离子辐射。 CMOS集成电路的布局显示可能需要高密度，不对称对接结CMOS反相器和其他CMOS电路的另一个接地规则的一个接地规则。
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公开(公告)号：US20130193513A1
公开(公告)日：2013-08-01
申请号：US13363651
申请日：2012-02-01
IPC分类号： H01L29/786 , G06F17/50 , H01L29/78
CPC分类号： H01L29/785 , H01L29/42376
摘要： A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.
摘要翻译： 一种多栅极场效应晶体管装置及其制造方法。 该装置包括源极端子，漏极端子和包括锥形栅极形状的栅极端子。 一种用于设计多栅极场效应晶体管的方法包括：设置具有锥形栅极剖面的源极端子，漏极端子和栅极端子，以在散热片的底部产生更宽的栅极宽度。
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公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。
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公开(公告)号：US09214529B2
公开(公告)日：2015-12-15
申请号：US13047132
申请日：2011-03-14
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。
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公开(公告)号：US08878298B2
公开(公告)日：2014-11-04
申请号：US13346165
申请日：2012-01-09
CPC分类号： H01L29/7856 , H01L29/66795
摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
摘要翻译： 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。
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