公开(公告)号：US07983175B2

公开(公告)日：2011-07-19

申请号：US12233724

申请日：2008-09-19

申请人： Martin J. Gale ,  Clare Owens ,  Peter Johnson ,  Jason Edmeades

发明人： Martin J. Gale ,  Clare Owens ,  Peter Johnson ,  Jason Edmeades

IPC分类号： H04L12/28

CPC分类号： H04L41/0677 ,  H04L43/50

摘要： A method and system detect a failed communication transmission that fails to reach a recipient after attempting to be transmitted from a sender to the recipient over a communication path. Upon detection of the failed communication, the method initiates a first inquiry process from the sender. This first inquiry process tests how far a first test communication transmission can travel from the sender to the recipient along the communication path. Similarly, upon detection of the failed communication, the method initiates a second inquiry process from the recipient. The second inquiry process tests how far a second test communication transmission can travel from the recipient to the sender along the communication path. The method combines the results of the first inquiry process and the results of the second inquiry process to determine which of the nodes in the communication path are not successfully forwarding test communications to identify at least one possibly faulty node. The identification of the possibly faulty node is then output to the sender and the recipient.

摘要翻译： 一种方法和系统检测在尝试通过通信路径从发送者发送到接收者之后，无法到达接收者的故障通信传输。 在检测到故障通信时，该方法从发送者发起第一询问处理。 该第一查询过程测试第一测试通信传输可以沿着通信路径从发送者到接收者的距离。 类似地，在检测到故障通信时，该方法从接收者发起第二个查询处理。 第二个查询过程测试第二个测试通信传输可以沿着通信路径从接收者到发送者的距离。 该方法将第一查询处理的结果和第二查询处理的结果相结合，以确定通信路径中的哪些节点不成功地转发测试通信以识别至少一个可能故障的节点。 然后将可能有故障的节点的识别输出到发送者和接收方。

公开(公告)号：US20100190311A1

公开(公告)日：2010-07-29

申请号：US12750145

申请日：2010-03-30

申请人： Peter Smeys ,  Peter Johnson

发明人： Peter Smeys ,  Peter Johnson

IPC分类号： H01L21/02

CPC分类号： H01F41/046 ,  B81B3/0072 ,  B81B2207/015 ,  H01F17/0006 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

摘要翻译： 通过在晶片的钝化层的顶表面上制造大量的MEMS器件，从而通过在钝化层和钝化层之间形成应力消除层来减小在每个管芯区域上形成MEMS器件的晶片中的弓 MEMS器件。

公开(公告)号：US20100079929A1

公开(公告)日：2010-04-01

申请号：US12243123

申请日：2008-10-01

申请人： Peter Smeys ,  Peter Johnson

发明人： Peter Smeys ,  Peter Johnson

IPC分类号： H01G9/07 ,  H01G9/00

CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01L21/02183 ,  H01L21/02258 ,  H01L21/31687 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

摘要： Integrated circuits structures and process sequences are provided for forming CMOS compatible high-density capacitors. The anodization of tantalum to tantalum oxide in the formation of the inter-plate capacitor dielectric results in very high dielectric constants since the defects usually found in the inter-plate dielectric are eliminated in the volume expansion that occurs during the oxidation of the tantalum material. This permits the fabrication of larger capacitors that can be incorporated into standard CMOS process flows.

摘要翻译： 集成电路结构和工艺顺序被提供用于形成CMOS兼容的高密度电容器。 在形成板间电容器电介质中，钽到氧化钽的阳极氧化导致非常高的介电常数，因为在钽材料的氧化期间发生的体积膨胀中消除了在板间电介质中通常发现的缺陷。 这允许制造可并入标准CMOS工艺流程的较大电容器。

公开(公告)号：US20100074118A1

公开(公告)日：2010-03-25

申请号：US12233724

申请日：2008-09-19

申请人： Martin J. Gale ,  Clare Owens ,  Peter Johnson ,  Jason Edmeades

发明人： Martin J. Gale ,  Clare Owens ,  Peter Johnson ,  Jason Edmeades

IPC分类号： H04L12/26

CPC分类号： H04L41/0677 ,  H04L43/50

摘要： A method and system detect a failed communication transmission that fails to reach a recipient after attempting to be transmitted from a sender to the recipient over a communication path. Upon detection of the failed communication, the method initiates a first inquiry process from the sender. This first inquiry process tests how far a first test communication transmission can travel from the sender to the recipient along the communication path. Similarly, upon detection of the failed communication, the method initiates a second inquiry process from the recipient. The second inquiry process tests how far a second test communication transmission can travel from the recipient to the sender along the communication path. The method combines the results of the first inquiry process and the results of the second inquiry process to determine which of the nodes in the communication path are not successfully forwarding test communications to identify at least one possibly faulty node. The identification of the possibly faulty node is then output to the sender and the recipient.

摘要翻译： 一种方法和系统检测在尝试通过通信路径从发送者发送到接收者之后，无法到达接收者的故障通信传输。 在检测到故障通信时，该方法从发送者发起第一询问处理。 该第一查询过程测试第一测试通信传输可以沿着通信路径从发送者到接收者的距离。 类似地，在检测到故障通信时，该方法从接收者发起第二个查询处理。 第二个查询过程测试第二个测试通信传输可以沿着通信路径从接收者到发送者的距离。 该方法将第一查询处理的结果和第二查询处理的结果相结合，以确定通信路径中的哪些节点不成功地转发测试通信以识别至少一个可能故障的节点。 然后将可能有故障的节点的识别输出到发送者和接收方。

公开(公告)号：US07584533B2

公开(公告)日：2009-09-08

申请号：US11973861

申请日：2007-10-10

申请人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

发明人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

IPC分类号： H01F3/00 ,  H01F41/02

CPC分类号： H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49144 ,  H01L2924/00

摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.

摘要翻译： 利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。 磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。 硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。 因此，由电感线圈产生的磁场与硬磁轴平行和自对准。 可以通过在平行于容易轴的施加磁场中电镀来增强易轴。

公开(公告)号：US07531824B1

公开(公告)日：2009-05-12

申请号：US11274932

申请日：2005-11-14

申请人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  William French

发明人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  William French

IPC分类号： H01L29/02

CPC分类号： H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/19015 ,  H01L2924/00

摘要： An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the conductor. The polymer material contains a ferromagnetic material so that the permeability of the polymer is greater than one. In various embodiments, the ferromagnetic material may be any one of a number of different high permeable materials such as iron oxide, zinc, manganese, zirconium, samarium (SA), neodymium (NA), cobalt, nickel or a combination thereof.

摘要翻译： 一种用于制造嵌入在半导体集成电路上的高值电感器的装置和方法。 该装置和方法包括在半导体衬底上形成导体。 一旦形成导体，在围绕导体的基底上提供聚合物材料。 聚合物材料含有铁磁材料，使得聚合物的渗透性大于1。 在各种实施方案中，铁磁材料可以是多种不同的高渗透性材料中的任何一种，例如氧化铁，锌，锰，锆，钐（SA），钕（NA），钴，镍或它们的组合。

公开(公告)号：US07528012B1

公开(公告)日：2009-05-05

申请号：US11508495

申请日：2006-08-22

申请人： Peter J. Hopper ,  Iouri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Iouri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L21/00

CPC分类号： H01L29/78606 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.

摘要翻译： 散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。 该装置包括形成在晶片的有源硅层中的晶体管。 活性表面形成在氧化物层和体硅层上。 在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。 在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。 塞子延伸穿过本体层的厚度到氧化物层。 此后，塞子填充有导热材料，例如金属或DAG（导热浆）。 在运行期间，来自晶体管的热量通过散热器消散。 在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。

公开(公告)号：US07463131B1

公开(公告)日：2008-12-09

申请号：US11111660

申请日：2005-04-21

申请人： Kyuwoon Hwang ,  Peter J. Hopper ,  Robert Drury ,  Peter Johnson

发明人： Kyuwoon Hwang ,  Peter J. Hopper ,  Robert Drury ,  Peter Johnson

IPC分类号： H01F5/00

CPC分类号： H02M7/003 ,  H01F1/14708 ,  H01F17/0006 ,  H01F17/04 ,  H01F2017/0066 ,  H01F2017/008 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.

摘要翻译： 片上电感器结构包括顶部和底部金属板，其形成为围绕形成在顶板和底板之间的导体线圈，但是通过介入材料与其分离。 顶板和底板优选地由铁磁合金形成，例如， 坡莫合金，并且被细分为多个间隔开的段，从而减少涡流。 基于用于制造结构的工艺技术来优化段的数量。 优选地，在顶板和底板之间形成有限的间隙，选择间隙的高度来调节结构的总电感。

公开(公告)号：US07331855B2

公开(公告)日：2008-02-19

申请号：US11484410

申请日：2006-07-11

申请人： Peter Johnson ,  Mark Pearson

发明人： Peter Johnson ,  Mark Pearson

IPC分类号： A01F12/49

CPC分类号： A01F12/40 ,  A01D41/1243

摘要： A chopper and wide-spread impeller spreader that feeds crop residue from the chopper into the spreader at a specific upward angle to more fully utilize the momentum the crop residue achieves in the chopper. The spreader incorporates air intake holes and air fins above the impellers to keep crop residue moving through the impellers without plugging of discharge material. The chopper propels the residue upwardly into the spreader resulting in a wide-spread broadcast, while preventing crop residue from plugging the spreader.

摘要翻译： 一种切碎机和广泛传播的叶轮撒布机，其将来自切碎机的作物残留物以特定的向上角度进料到扩展器中，以更充分地利用作物残渣在切碎机中实现的动量。 吊具将进气孔和叶轮上方的空气翅片结合在一起，以保持作物残留物在叶轮上移动而不会堵塞排料。 切碎机将残留物向上推入撒布机，导致广泛的广播，同时防止作物残留物堵塞吊具。

公开(公告)号：US07301436B1

公开(公告)日：2007-11-27

申请号：US11274491

申请日：2005-11-14

申请人： Peter J. Hopper ,  Peter Johnson ,  Philipp Lindorfer

发明人： Peter J. Hopper ,  Peter Johnson ,  Philipp Lindorfer

IPC分类号： H01C13/00

CPC分类号： H01L23/5228 ,  H01L24/02 ,  H01L27/0802 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043

摘要： An apparatus and method for using anti-fuse bond pads used to provide trimmed resistor values to the input terminals of circuits on an integrated circuit die. The apparatus and method comprises fabricating on a semiconductor integrated circuit a resistive network. The resistive network includes a first terminal, a second terminal and a resistor coupled between the two terminals. An anti-fuse bond pad and a trimming resistor are coupled between the first terminal and the second terminal. The trimming resistor is configured to be electrically coupled between the first terminal and the second terminal when a ball bond is formed on the anti-fuse bond pad. In various embodiments, a plurality of the anti-fuse bond pads and trimming resistors may be coupled between the two terminals. By selectively forming ball bonds on the plurality of anti-fuse bond pads, the resistance of the network can be selectively trimmed as needed.

摘要翻译： 一种用于使用反熔丝接合焊盘的装置和方法，用于向集成电路管芯上的电路的输入端提供修整的电阻值。 该装置和方法包括在半导体集成电路上制造电阻网络。 电阻网络包括耦合在两个端子之间的第一端子，第二端子和电阻器。 反熔丝接合焊盘和微调电阻耦合在第一端子和第二端子之间。 当在反熔丝接合焊盘上形成球焊时，微调电阻被配置为电耦合在第一端子和第二端子之间。 在各种实施例中，多个反熔丝接合焊盘和微调电阻器可以耦合在两个端子之间。 通过在多个反熔丝接合焊盘上选择性地形成球键，可以根据需要选择性地修整网络的电阻。