公开(公告)号：US11782863B2

公开(公告)日：2023-10-10

申请号：US17826056

申请日：2022-05-26

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/00

Abstract: A memory module includes memory devices and a configurable command buffer that selects between alternative command ports for controlling different groupings of the memory devices. Memory systems with memory modules incorporating such a command buffer and memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths.

公开(公告)号：US11587605B2

公开(公告)日：2023-02-21

申请号：US17341048

申请日：2021-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20230052053A1

公开(公告)日：2023-02-16

申请号：US17849450

申请日：2022-06-24

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20220374381A1

公开(公告)日：2022-11-24

申请号：US17826056

申请日：2022-05-26

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16

Abstract: A memory module includes memory devices and a configurable command buffer that selects between alternative command ports for controlling different groupings of the memory devices. Memory systems with memory modules incorporating such a command buffer and memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths.

公开(公告)号：US20220261361A1

公开(公告)日：2022-08-18

申请号：US17568645

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Frederick A. Ware ,  Brent S. Haukness

IPC: G06F13/16 ,  G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

公开(公告)号：US20190102327A1

公开(公告)日：2019-04-04

申请号：US16145837

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US10026466B2

公开(公告)日：2018-07-17

申请号：US15616209

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/32 ,  G06F1/04 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20170371827A1

公开(公告)日：2017-12-28

申请号：US15647983

申请日：2017-07-12

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G06F13/16 ,  G11C11/4094 ,  G11C11/4093 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US09715467B2

公开(公告)日：2017-07-25

申请号：US14080724

申请日：2013-11-14

Applicant: RAMBUS INC.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20150162061A1

公开(公告)日：2015-06-11

申请号：US14325140

申请日：2014-07-07

Applicant: RAMBUS INC.

Inventor： Liji Gopalakrishnan ,  Mahabaleshwara Mahabaleshwara

IPC: G11C7/22 ,  G11C29/02

CPC classification number: G11C29/023 ,  G06F11/1076 ,  G06F11/14 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028

Abstract: A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.

Abstract translation: 存储器控制器包括用于确定一个或多个存储器件的相应参考电压值和延迟值的逻辑。 存储器控制器包括命令地址（CA）接口，用于向存储器件发送命令以将存储器件的参考电压值设置为测试值，数据接口将数据模式写入存储器件并读取 来自存储器件的数据模式，以及测试参考电压逻辑，以对从存储器件读取的数据模式的至少一部分执行密度检查，并且基于密度检查确定测试值是否是潜在的参考电压值。 可以使用从一个或多个潜在参考电压值中选择的操作参考电压值来确定延迟值。