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公开(公告)号：US07982646B2
公开(公告)日：2011-07-19
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/00
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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公开(公告)号：US07868645B2
公开(公告)日：2011-01-11
申请号：US12774305
申请日：2010-05-05
IPC分类号： H03K19/195
CPC分类号： H03K19/1954 , B82Y10/00 , G06N99/002 , H03K17/92 , H03K19/0008 , H03K19/1952 , H03K2217/0036
摘要： In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.
摘要翻译： 在一个实施例中，本公开涉及由AC电源供电的单通量量子（SFQ）信号传输线。 交流电源向具有初级绕组和次级绕组的变压器供电。 初级绕组接收AC信号，次级绕组将信号传送到SFQ传输线。 传输线可以可选地包括用于接收进入的SFQ脉冲的输入滤波器电路。 滤波电路可以具有并联连接的电阻器和电感器。 在替代布置中，滤波器电路可以包括电感器。 第一个约瑟夫逊结可以连接到滤波电路和次级绕组。 约瑟夫逊连接点响应于输入的SFQ脉冲触发并响应于来自次级绕组的功率放电而重新产生脉冲信号。
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公开(公告)号：US07772871B2
公开(公告)日：2010-08-10
申请号：US12111035
申请日：2008-04-28
IPC分类号： H03K19/195
CPC分类号： H03K3/38
摘要： The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.
摘要翻译： 本公开涉及提供逻辑电路元件的方法。 该方法包括在第一约瑟夫逊结和第二约瑟夫逊结之间布置一系列约瑟夫逊结，第一约瑟夫逊结具有第一临界电流（Ic1），第二约瑟夫逊结具有第二临界电流（Ic2）; 向第一个约瑟夫逊结提供工作电流，工作电流通过一系列约瑟夫逊路传输到第二个约瑟夫逊路口; 其中工作电流足够高以触发第二约瑟夫逊结，同时足够低以不干扰一系列中间约瑟夫逊结的超导电性。
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公开(公告)号：US07724020B2
公开(公告)日：2010-05-25
申请号：US11956293
申请日：2007-12-13
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H03K19/195
CPC分类号： H03K19/1952 , B82Y10/00 , G06N99/002 , H03K17/92 , H03K19/0008 , H03K2217/0036
摘要： Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.
摘要翻译： 本文公开了超导单通量量子电路，每个具有至少一个约瑟夫逊结，当通过其的电流超过临界电流时，其将翻转。 约瑟夫逊结的偏置电流由偏置变压器代替电阻器提供。 缺少任何偏置电阻器可确保消除不必要的功耗。
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公开(公告)号：US20090267635A1
公开(公告)日：2009-10-29
申请号：US12111035
申请日：2008-04-28
IPC分类号： H03K19/195
CPC分类号： H03K3/38
摘要： The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.
摘要翻译： 本公开涉及提供逻辑电路元件的方法。 该方法包括在第一约瑟夫逊结和第二约瑟夫逊结之间布置一系列约瑟夫逊结，第一约瑟夫逊结具有第一临界电流（Ic1），第二约瑟夫逊结具有第二临界电流（Ic2）; 向第一个约瑟夫逊结提供工作电流，工作电流通过一系列约瑟夫逊路传输到第二个约瑟夫逊路口; 其中工作电流足够高以触发第二约瑟夫逊结，同时足够低以不干扰一系列中间约瑟夫逊结的超导电性。
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公开(公告)号：US06917216B2
公开(公告)日：2005-07-12
申请号：US10411106
申请日：2003-04-11
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H03F19/00 , H03K3/38 , H03K5/02 , H03K19/195
摘要： A single flux quantum (SFQ) pulse is generated (502) by injecting a superconductor output signal as a first signal at a “start” input (108) coupled to a superconductor delay element (104). The SFQ pulse is reflected (504) back and forth between first and second superconductor reflectors (102, 106) coupled to opposite ends of the superconductor delay element, thereby generating a time-disperse plurality of SFQ pulses at an output (110) coupled to the superconductor delay element. Thereafter, a second signal is input at a “stop” input (112) coupled to one of the first and second superconductor reflectors, thereby interrupting (506) the reflecting of the SFQ pulse at the one of the first and second superconductor reflectors, thus ending the generating of the time-disperse plurality of SFQ pulses at the output.
摘要翻译： 通过在与超导体延迟元件（104）耦合的“起始”输入端（108）处注入超导体输出信号作为第一信号来产生单通量量（SFQ）脉冲（502）。 SFQ脉冲在耦合到超导体延迟元件的相对端的第一和第二超导体反射器（102,106）之间来回反射（504），从而在耦合到超导体延迟元件的输出端（110）处产生时间分散的多个SFQ脉冲 超导体延迟元件。 此后，在耦合到第一和第二超导体反射器中的一个的“停止”输入端（112）处输入第二信号，从而中断（506）第一和第二超导体反射器之一处的SFQ脉冲的反射，从而 结束在输出端产生时间分散的多个SFQ脉冲。
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77.发明授权Superconducting digital first-in first-out buffer using physical back pressure mechanism 失效超导数字先进先出缓冲器采用物理背压机构公开(公告)号：US06909109B2
公开(公告)日：2005-06-21
申请号：US10628779
申请日：2003-07-28
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： G06F5/08 , G11C19/32 , H01L29/06 , H01L31/0256 , H01L39/22
摘要： A digital first-in first-out (FIFO) buffer (10) for use with Single Flux Quantum (SFQ) superconductive integrated circuits. The digital FIFO buffer (10) includes a clock-storage circuit (14) for receiving and storing load and read clock signals (100, 104) and a data-storage circuit (16) connected to the clock-storage circuit (14) for receiving and storing data signal pulses (102) in the order which the data signal pulses (102) are received relative to the load clock signal (100). The data-storage circuit (16) outputs the SFQ pulse signal independent of the load clock signal (100). The previously stored clock and data signal pulses (100, 102) provide physical back pressure to their subsequent signal pulses.
摘要翻译： 用于单通量量子（SFQ）超导集成电路的数字先进先出（FIFO）缓冲器（10）。 数字FIFO缓冲器（10）包括用于接收和存储负载和读时钟信号（100,104）的时钟存储电路（14）和连接到时钟存储电路（14）的数据存储电路（16），用于 以数据信号脉冲（102）相对于负载时钟信号（100）的顺序接收和存储数据信号脉冲（102）。 数据存储电路（16）独立于负载时钟信号（100）输出SFQ脉冲信号。 先前存储的时钟和数据信号脉冲（100,102）为其后续的信号脉冲提供物理背压。
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公开(公告)号：US06865639B2
公开(公告)日：2005-03-08
申请号：US10028049
申请日：2001-12-19
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H04L12/931 , H04L12/933 , G06F13/00
CPC分类号： H04L49/101 , H04L49/45
摘要： A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data input. A serial address and data enter the address input and the data input in parallel. A shift sequence is transmitted on the single shift input. The data flows before the shift sequence on the shift input is complete. The data is shifted through the crossbar switch using a clock that is generated on-chip using a clock recovery circuit. The decoder converts a binary address input into a serial address and includes an N-bit counter with a plurality of toggle flip-flops. The crossbar switch is implemented using superconductor digital electronics such as rapid single flux quantum (RSFQ) logic.
摘要翻译： 交叉开关包括交叉点矩阵，其具有n个输入行的交叉点和m个输出列的交叉点。 交叉开关还包括连接到n个输入行的n个解码器。 n行中的每一行包括单个串行地址输入，移位输入和数据输入。 串行地址和数据并行输入地址输入和数据输入。 在单个移位输入端发送一个移位序列。 数据在移位输入的移位顺序完成之前流动。 数据通过使用时钟恢复电路的芯片上产生的时钟通过交叉开关进行移位。 解码器将二进制地址输入转换为串行地址，并且包括具有多个开锁触发器的N位计数器。 交叉开关使用超导体数字电子设备实现，例如快速单通量量子（RSFQ）逻辑。
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公开(公告)号：US06759974B1
公开(公告)日：2004-07-06
申请号：US10441842
申请日：2003-05-20
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H03M734
CPC分类号： H03K5/135
摘要： A decoder for decoding data transmitted between superconductor circuits. Interleaved data and clock pulses are applied to a clock input of a flip-flop circuit and one input of an AND gate. The output of the flip-flop circuit is a clock signal, and is applied to a delay circuit to be put in phase with the data pulses in the interleaved signal. The delayed clock signal is then applied to the other input of the AND gate, so that when a data pulse occurs in the interleaved signal it aligns with a clock pulse and is outputted from the AND gate. The clock signal from the flip-flop circuit is also sent to the input of the flip-flop circuit through a delay circuit that delays the signal more than one half of the clock period and less than one clock period. This delayed clock signal sets the flip-flop circuit to the “1” state after the data pulse in the interleaved signal are input to the flip-flop circuit so that the data pulses are not outputted from the flip-flop circuit.
摘要翻译： 一种用于解码在超导体电路之间传输的数据的解码器。 交错数据和时钟脉冲被施加到触发电路的时钟输入和与门的一个输入。 触发器电路的输出是时钟信号，并且被施加到延迟电路以与交错信号中的数据脉冲同相。 延迟的时钟信号然后被施加到与门的另一个输入端，这样当交错信号发生数据脉冲时，它与时钟脉冲对齐并从与门输出。 来自触发器电路的时钟信号也通过一个延迟电路发送到触发器电路的输入，该延迟电路延迟了时钟周期的一半以上且小于一个时钟周期。 该延迟时钟信号在交错信号中的数据脉冲被输入到触发电路之后将触发器电路设置为“1”状态，使得数据脉冲不从触发器电路输出。
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80.发明授权Transmission line single flux quantum chip-to -chip communication with flip-chip bump transitions 失效传输线单通量子芯片到芯片通信与倒装芯片突发过渡公开(公告)号：US06678540B2
公开(公告)日：2004-01-13
申请号：US09935037
申请日：2001-08-22
申请人： Michael S. Wire , Quentin P. Herr
发明人： Michael S. Wire , Quentin P. Herr
IPC分类号： H01P100
CPC分类号： H01P1/047 , Y10S505/70 , Y10S505/703 , Y10S505/706
摘要： A superconductor on-chip microstrip line (2, 4) to off-chip microstrip line (7) transition of low characteristic impedance (15, 20, 22) is realized that obtains a bandwidth of 200 GHz for MCM application while employing solder bump (15, 17) technology to connect the chips (3, 5) to the off-chip microstrip and substrate (6). Circular openings (20, 22) through the respective ground plane layers (10 & 16) of the off-chip and on-chip microstrips are provided in positions respectively underlying and overlying the solder bump (15) for the signal. The openings may be sized to provide a desired ratio of inductance to capacitance, the larger the size, the greater the ratio value. This technique may be used to match characteristic impedance to give broad bandwidth low impedance interconnections needed for direct SFQ chip-to-chip communication on a passive MCM.
摘要翻译： 实现了超导体片上微带线（2,4）到片外微带线（7）低特性阻抗（15,20,22）的转换，在采用焊料凸块时获得了MCM应用的200 GHz带宽（ 将芯片（3,5）连接到片外微带和基板（6）的技术。 提供片外微芯片的各个接地平面层（10和16）的圆形开口（20,22）分别设置在用于信号的焊料凸点（15）的下面和上方的位置上。 开口的尺寸可以提供所需的电感与电容的比例，尺寸越大，比值越大。 该技术可用于匹配特性阻抗，以提供无源MCM上直接SFQ芯片到芯片通信所需的宽带宽低阻抗互连。
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