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公开(公告)号：US20100026538A1
公开(公告)日：2010-02-04
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/02
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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公开(公告)号：US07982646B2
公开(公告)日：2011-07-19
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/00
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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3.发明申请METHOD AND APPARATUS FOR CONTROLLING QUBITS WITH SINGLE FLUX QUANTUM LOGIC 有权用单通道量子逻辑控制QUBITS的方法和装置公开(公告)号：US20110133770A1
公开(公告)日：2011-06-09
申请号：US13022276
申请日：2011-02-07
申请人： John Xavier PRZYBYSZ , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
发明人： John Xavier PRZYBYSZ , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
IPC分类号： H03K19/195
CPC分类号： B82Y10/00 , G06N99/002
摘要： In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.
摘要翻译： 在一个实施例中，本公开涉及通过将量子位耦合到通量量子逻辑门来使量子比特进入和退出谐振来控制量子位的能量状态的方法和装置。 量子位可以与泵浦信号共振，具有另一个量子位或一些量子逻辑门。 在另一个实施例中，本公开涉及一种用RSFQ逻辑或通过RSFQ与量子比特之间的接口来控制量子比特的方法。
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4.发明授权公开(公告)号：US08138784B2
公开(公告)日：2012-03-20
申请号：US13022276
申请日：2011-02-07
申请人： John Xavier Przybysz , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
发明人： John Xavier Przybysz , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
IPC分类号： H03K19/195
CPC分类号： B82Y10/00 , G06N99/002
摘要： In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.
摘要翻译： 在一个实施例中，本公开涉及通过将量子位耦合到通量量子逻辑门来使量子比特进入和退出谐振来控制量子位的能量状态的方法和装置。 量子位可以与泵浦信号共振，具有另一个量子位或一些量子逻辑门。 在另一个实施例中，本公开涉及一种用RSFQ逻辑或通过RSFQ与量子比特之间的接口来控制量子比特的方法。
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公开(公告)号：US09905900B2
公开(公告)日：2018-02-27
申请号：US14702044
申请日：2015-05-01
IPC分类号： H03K19/195 , H01P3/06 , H03K3/38
CPC分类号： H01P3/06 , H03K3/38 , H03K19/195
摘要： A microwave circuit is provided that comprises a plurality of transmission lines each configured to receive and propagate a respective waveform signal of a plurality of waveform signals, and a combiner that receives and combines the plurality of waveform signals from outputs of the plurality of transmission lines into a combined output waveform signal that is output terminated by an output termination resistor. The microwave circuit further comprises a compensation signal generator that generates a compensation signal to mitigate reflections associated with the transmission of signals through the microwave circuit.
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公开(公告)号：US07772871B2
公开(公告)日：2010-08-10
申请号：US12111035
申请日：2008-04-28
IPC分类号： H03K19/195
CPC分类号： H03K3/38
摘要： The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.
摘要翻译： 本公开涉及提供逻辑电路元件的方法。 该方法包括在第一约瑟夫逊结和第二约瑟夫逊结之间布置一系列约瑟夫逊结，第一约瑟夫逊结具有第一临界电流（Ic1），第二约瑟夫逊结具有第二临界电流（Ic2）; 向第一个约瑟夫逊结提供工作电流，工作电流通过一系列约瑟夫逊路传输到第二个约瑟夫逊路口; 其中工作电流足够高以触发第二约瑟夫逊结，同时足够低以不干扰一系列中间约瑟夫逊结的超导电性。
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公开(公告)号：US20090267635A1
公开(公告)日：2009-10-29
申请号：US12111035
申请日：2008-04-28
IPC分类号： H03K19/195
CPC分类号： H03K3/38
摘要： The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.
摘要翻译： 本公开涉及提供逻辑电路元件的方法。 该方法包括在第一约瑟夫逊结和第二约瑟夫逊结之间布置一系列约瑟夫逊结，第一约瑟夫逊结具有第一临界电流（Ic1），第二约瑟夫逊结具有第二临界电流（Ic2）; 向第一个约瑟夫逊结提供工作电流，工作电流通过一系列约瑟夫逊路传输到第二个约瑟夫逊路口; 其中工作电流足够高以触发第二约瑟夫逊结，同时足够低以不干扰一系列中间约瑟夫逊结的超导电性。
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公开(公告)号：US11333413B2
公开(公告)日：2022-05-17
申请号：US16554203
申请日：2019-08-28
申请人： Robert Miles Young , Aaron Ashley Hathaway , John X. Przybysz , Gregory R. Boyd , Zachary A. Stegen , Edward R. Engbrecht , Aaron A. Pesetski , Marc Eisenzweig Sherwin
发明人： Robert Miles Young , Aaron Ashley Hathaway , John X. Przybysz , Gregory R. Boyd , Zachary A. Stegen , Edward R. Engbrecht , Aaron A. Pesetski , Marc Eisenzweig Sherwin
摘要： A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.
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公开(公告)号：US20210063060A1
公开(公告)日：2021-03-04
申请号：US16554203
申请日：2019-08-28
申请人： Robert Miles Young , Aaron Ashley Hathaway , John X. Przybysz , Gregory R. Boyd , Zachary A. Stegen , Edward R. Engbrecht , Aaron A. Pesetski , Marc Eisenzweig Sherwin
发明人： Robert Miles Young , Aaron Ashley Hathaway , John X. Przybysz , Gregory R. Boyd , Zachary A. Stegen , Edward R. Engbrecht , Aaron A. Pesetski , Marc Eisenzweig Sherwin
摘要： A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.
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公开(公告)号：US09035704B2
公开(公告)日：2015-05-19
申请号：US12896349
申请日：2010-10-01
CPC分类号： B82Y10/00 , H01L2223/6655 , H03F3/04
摘要： High impedance, high frequency nanoscale device electronics configured to interface with low impedance loads include an impedance transforming stage constructed of multiple nanoscale devices, such as carbon nanotube field-effect transistors. In an embodiment of the present invention, an impedance transforming output stage of a multistage amplifier is configured to drive a 50 ohm transmission line with unity voltage gain using multiple carbon nanotube field-effect transistors in parallel. In a further embodiment, a receiver provided for an electronically steered receive array is a monolithic, lumped-element system formed from nanoscale devices and configured to interface with the external electrical systems via a single transmission line.
摘要翻译： 配置为与低阻抗负载相连接的高阻抗，高频纳米级器件电子器件包括由多个纳米尺度器件（例如碳纳米管场效应晶体管）构成的阻抗变换级。 在本发明的一个实施例中，多级放大器的阻抗变换输出级配置为并联使用多个碳纳米管场效应晶体管驱动具有单位电压增益的50欧姆传输线。 在另一个实施例中，为电子转向接收阵列提供的接收器是由纳米级器件形成的单片式集总元件系统，并被配置为经由单个传输线与外部电气系统接口。
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