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公开(公告)号：US20100026538A1
公开(公告)日：2010-02-04
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/02
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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公开(公告)号：US07982646B2
公开(公告)日：2011-07-19
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/00
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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3.发明申请METHOD AND APPARATUS FOR CONTROLLING QUBITS WITH SINGLE FLUX QUANTUM LOGIC 有权用单通道量子逻辑控制QUBITS的方法和装置公开(公告)号：US20110133770A1
公开(公告)日：2011-06-09
申请号：US13022276
申请日：2011-02-07
申请人： John Xavier PRZYBYSZ , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
发明人： John Xavier PRZYBYSZ , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
IPC分类号： H03K19/195
CPC分类号： B82Y10/00 , G06N99/002
摘要： In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.
摘要翻译： 在一个实施例中，本公开涉及通过将量子位耦合到通量量子逻辑门来使量子比特进入和退出谐振来控制量子位的能量状态的方法和装置。 量子位可以与泵浦信号共振，具有另一个量子位或一些量子逻辑门。 在另一个实施例中，本公开涉及一种用RSFQ逻辑或通过RSFQ与量子比特之间的接口来控制量子比特的方法。
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4.发明授权公开(公告)号：US08138784B2
公开(公告)日：2012-03-20
申请号：US13022276
申请日：2011-02-07
申请人： John Xavier Przybysz , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
发明人： John Xavier Przybysz , James E. Baumgardner , Aaron A. Pesetski , Donald Lynn Miller , Quentin P. Herr
IPC分类号： H03K19/195
CPC分类号： B82Y10/00 , G06N99/002
摘要： In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.
摘要翻译： 在一个实施例中，本公开涉及通过将量子位耦合到通量量子逻辑门来使量子比特进入和退出谐振来控制量子位的能量状态的方法和装置。 量子位可以与泵浦信号共振，具有另一个量子位或一些量子逻辑门。 在另一个实施例中，本公开涉及一种用RSFQ逻辑或通过RSFQ与量子比特之间的接口来控制量子比特的方法。
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公开(公告)号：US09905900B2
公开(公告)日：2018-02-27
申请号：US14702044
申请日：2015-05-01
IPC分类号： H03K19/195 , H01P3/06 , H03K3/38
CPC分类号： H01P3/06 , H03K3/38 , H03K19/195
摘要： A microwave circuit is provided that comprises a plurality of transmission lines each configured to receive and propagate a respective waveform signal of a plurality of waveform signals, and a combiner that receives and combines the plurality of waveform signals from outputs of the plurality of transmission lines into a combined output waveform signal that is output terminated by an output termination resistor. The microwave circuit further comprises a compensation signal generator that generates a compensation signal to mitigate reflections associated with the transmission of signals through the microwave circuit.
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公开(公告)号：US07772871B2
公开(公告)日：2010-08-10
申请号：US12111035
申请日：2008-04-28
IPC分类号： H03K19/195
CPC分类号： H03K3/38
摘要： The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.
摘要翻译： 本公开涉及提供逻辑电路元件的方法。 该方法包括在第一约瑟夫逊结和第二约瑟夫逊结之间布置一系列约瑟夫逊结，第一约瑟夫逊结具有第一临界电流（Ic1），第二约瑟夫逊结具有第二临界电流（Ic2）; 向第一个约瑟夫逊结提供工作电流，工作电流通过一系列约瑟夫逊路传输到第二个约瑟夫逊路口; 其中工作电流足够高以触发第二约瑟夫逊结，同时足够低以不干扰一系列中间约瑟夫逊结的超导电性。
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公开(公告)号：US20090267635A1
公开(公告)日：2009-10-29
申请号：US12111035
申请日：2008-04-28
IPC分类号： H03K19/195
CPC分类号： H03K3/38
摘要： The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.
摘要翻译： 本公开涉及提供逻辑电路元件的方法。 该方法包括在第一约瑟夫逊结和第二约瑟夫逊结之间布置一系列约瑟夫逊结，第一约瑟夫逊结具有第一临界电流（Ic1），第二约瑟夫逊结具有第二临界电流（Ic2）; 向第一个约瑟夫逊结提供工作电流，工作电流通过一系列约瑟夫逊路传输到第二个约瑟夫逊路口; 其中工作电流足够高以触发第二约瑟夫逊结，同时足够低以不干扰一系列中间约瑟夫逊结的超导电性。
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8.发明授权Superconducting phase-controlled hysteretic magnetic Josephson junction JMRAM memory cell 有权超导相控滞后磁约瑟夫逊结JMRAM记忆单元公开(公告)号：US09520181B1
公开(公告)日：2016-12-13
申请号：US14854994
申请日：2015-09-15
申请人： Donald L. Miller , Andrew Hostetler Miklich , Anna Y. Herr , Quentin P. Herr , William Robert Reohr
发明人： Donald L. Miller , Andrew Hostetler Miklich , Anna Y. Herr , Quentin P. Herr , William Robert Reohr
CPC分类号： G11C11/44 , G11C11/16 , G11C11/1673 , G11C11/1675
摘要： One embodiment describes a JMRAM memory cell system. The system includes a phase hysteretic magnetic Josephson junction (PHMJJ) that stores one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state. The system also includes a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state. The system further includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.
摘要翻译： 一个实施例描述了JMRAM存储器单元系统。 该系统包括相位滞后磁约瑟夫逊结（PHMJJ），其响应于在数据写入操作期间提供的写入电流而存储第一二进制状态和第二二进制状态之一，并且基于所存储的数字状态提供超导相位。 该系统还包括定向写入元件，其被配置为在数据写入操作期间提供方向偏置电流，以在对应于第一二进制状态的预定方向上提供PHMJJ的超导相位。 该系统还包括至少一个约瑟夫逊结，其具有基于PHMJJ的超导相位的临界电流，并且被配置为响应于在读取操作期间提供的读取电流来提供对应于存储的数字状态的输出。
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公开(公告)号：US10367483B1
公开(公告)日：2019-07-30
申请号：US16227883
申请日：2018-12-20
IPC分类号： H03K3/38 , G06N10/00 , H03K19/195 , H02M7/04
摘要： One embodiment describes a Josephson current source system comprising a flux-shuttle loop that is inductively coupled with an AC input signal. The flux-shuttle loop includes a plurality of stages each comprising at least one Josephson junction. The plurality of stages can be spaced about the flux shuttle loop. Each of a plurality of pairs of the plurality of stages are configured to concurrently trigger in a sequence via the respective at least one Josephson junction in response to the AC input signal and to provide a respective pair of single-flux quantum (SFQ) pulses that move sequentially and continuously through each stage of the plurality of stages around the flux-shuttle loop via each of the at least one Josephson junction of each of the respective stages that results in a DC output current being provided through an output inductor.
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公开(公告)号：US11476842B1
公开(公告)日：2022-10-18
申请号：US17350712
申请日：2021-06-17
IPC分类号： H03K3/38 , G06N10/00 , H03K19/195
摘要： One example describes a superconducting current source system comprising a linear flux-shuttle. The linear flux-shuttle includes an input and a plurality of Josephson transmission line (JTL) stages. Each of the JTL stages includes at least one Josephson junction, an output inductor, and a clock input. The linear flux-shuttle can be configured to generate a direct current (DC) output current via the output inductor associated with each of the JTL stages in response to the at least one Josephson junction triggering in a sequence in each of the JTL stages along the linear flux-shuttle in response to receiving an input pulse at the input and in response to a clock signal provided to the clock input in each of the JTL stages.
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