Dynamic monitoring of ability to reassemble streaming data across multiple channels based on history
    71.
    发明授权
    Dynamic monitoring of ability to reassemble streaming data across multiple channels based on history 有权
    根据历史,跨多个渠道重新组合流数据的能力的动态监控

    公开(公告)号:US08489967B2

    公开(公告)日:2013-07-16

    申请号:US13438227

    申请日:2012-04-03

    IPC分类号: H03M13/00

    摘要: Mechanisms are provided for processing streaming data at high sustained data rates. These mechanisms receive a plurality of data elements over a plurality of non-sequential communication channels and write the plurality of data elements directly to the file system of the data processing system in an unassembled manner. The mechanisms determining whether to perform a data scrubbing operation or not based on history information indicative of whether data elements in the plurality of data elements are being received in a substantially sequential manner. The mechanisms perform a data scrubbing operation, in response to a determination to perform data scrubbing, to identify any missing data elements in the plurality of data elements written to the file system and assemble the plurality of data elements into a plurality of data streams in response to results of the data scrubbing indicating that there are no missing data elements.

    摘要翻译: 提供了用于以高持续数据速率处理流数据的机制。 这些机制通过多个非顺序通信信道接收多个数据元素,并以未组装的方式将多个数据元素直接写入数据处理系统的文件系统。 基于表示多个数据元素中的数据元素是否以大致顺序的方式被接收的历史信息,确定是否执行数据擦除操作的机制。 响应于执行数据擦除的确定,机构执行数据擦除操作以识别写入文件系统的多个数据元素中的任何丢失的数据元素,并将多个数据元素组合成多个数据流以作为响应 到数据清理的结果,表明没有丢失的数据元素。

    Speculative popcount data creation
    72.
    发明授权
    Speculative popcount data creation 有权
    投机性的popcount数据创建

    公开(公告)号:US08387065B2

    公开(公告)日:2013-02-26

    申请号:US12425343

    申请日:2009-04-16

    摘要: A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.

    摘要翻译: 一种方法和数据处理系统,通过该方法和数据处理系统有效地执行人口计数(popcount)操作,而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。 该方法包括:识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下,作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。 该方法还包括:确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。

    Management of process-to-process intra-cluster communication requests
    73.
    发明授权
    Management of process-to-process intra-cluster communication requests 失效
    管理流程到流程的群集间通信请求

    公开(公告)号:US08370855B2

    公开(公告)日:2013-02-05

    申请号:US12342616

    申请日:2008-12-23

    IPC分类号: G06F9/52

    CPC分类号: G06F9/545 G06F9/547

    摘要: A mechanism is provided for managing a process-to-process intra-cluster communication request. A call from a first application is received in a first operating system in a first data processing system. The first operating system passes the call from the first operating system to a first host fabric interface controller in the first data processing system without processing the call. The first host fabric interface controller processes the call without intervention by the first operating system to determine a second data processing system in the plurality of data processing systems with which the call is associated. The first host fabric interface controller initiates an intra-cluster connection to a second host fabric interface controller in the second data processing system. The first host fabric interface controller then transfers the call to the second host fabric interface controller in the second data processing system via the intra-cluster connection.

    摘要翻译: 提供了一种用于管理流程到流程的群集内通信请求的机制。 在第一数据处理系统中的第一操作系统中接收来自第一应用的呼叫。 第一操作系统将呼叫从第一操作系统传递到第一数据处理系统中的第一主机结构接口控制器,而不处理该呼叫。 所述第一主机结构接口控制器处理所述呼叫而不用所述第一操作系统进行干预以确定所述呼叫与之相关联的所述多个数据处理系统中的第二数据处理系统。 第一主机结构接口控制器在第二数据处理系统中发起到第二主机结构接口控制器的集群内连接。 第一主机接口控制器然后经由集群内连接将呼叫转移到第二数据处理系统中的第二主机结构接口控制器。

    Reassembling streaming data across multiple packetized communication channels
    75.
    发明授权
    Reassembling streaming data across multiple packetized communication channels 有权
    在多个分组化通信信道上重新组合流数据

    公开(公告)号:US08335238B2

    公开(公告)日:2012-12-18

    申请号:US12342193

    申请日:2008-12-23

    IPC分类号: H04J3/00

    摘要: Mechanisms are provided for processing streaming data at high sustained data rates. These mechanisms receive a plurality of data elements over a plurality of non-sequential communication channels and write the plurality of data elements directly to the file system of the data processing system in an unassembled manner. The mechanisms further perform a data scrubbing operation to determine if there are any missing data elements that are not present in the plurality of data elements written to the file system and assemble the plurality of data elements into a plurality of data streams associated with the plurality of non-sequential communication channels in response to results of the data scrubbing indicating that there are no missing data elements. In addition, the mechanisms release the assembled plurality of data streams for access via the file system.

    摘要翻译: 提供了用于以高持续数据速率处理流数据的机制。 这些机制通过多个非顺序通信信道接收多个数据元素,并以未组装的方式将多个数据元素直接写入数据处理系统的文件系统。 所述机构还执行数据擦除操作以确定是否存在写入所述文件系统的所述多个数据元素中不存在的丢失的数据元素,并将所述多个数据元素组合成与所述多个数据元素相关联的多个数据流 响应于指示没有丢失数据元素的数据擦除的结果的非顺序通信信道。 此外,这些机制释放组合的多个数据流以便经由文件系统访问。

    Look-ahead wake-and-go engine with speculative execution
    76.
    发明授权
    Look-ahead wake-and-go engine with speculative execution 有权
    具有推测性执行的前瞻式唤醒引擎

    公开(公告)号:US08316218B2

    公开(公告)日:2012-11-20

    申请号:US12024419

    申请日:2008-02-01

    IPC分类号: G06F9/00

    摘要: A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicate that the thread is waiting for an event. if a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the corresponding idiom so that the wake-and-go mechanism may have the thread perform speculative execution at a time when the thread is waiting for an event. During execution, when the wake-and-go mechanism recognizes a programming idiom, the wake-and-go mechanism may store the thread state in the thread state storage. Instead of putting the thread to sleep, the wake-and-go mechanism may perform speculative execution.

    摘要翻译: 为微处理器提供唤醒机制。 唤醒机制在用于编程习惯的线程的指令流中预示着线程正在等待事件。 如果先行轮询操作成功,则先行唤醒引导引擎可以记录相应成语的指令地址,使得唤醒机制可以使线程在线程执行推测性执行 正在等待一个事件。 在执行期间,当唤醒机制识别出编程习惯时,唤醒机制可以将线程状态存储在线程状态存储器中。 唤醒机制可以执行推测性的执行,而不是让线程睡觉。

    Block driven computation with an address generation accelerator
    77.
    发明授权
    Block driven computation with an address generation accelerator 失效
    使用地址生成加速器进行块驱动计算

    公开(公告)号:US08285971B2

    公开(公告)日:2012-10-09

    申请号:US12336315

    申请日:2008-12-16

    IPC分类号: G06F12/00

    摘要: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.

    摘要翻译: 处理器包括执行指令的至少一个执行单元,耦合到所述至少一个执行单元的至少一个寄存器文件,其缓冲由所述至少一个执行单元访问的操作数,指令排序单元,其通过 所述至少一个执行单元和地址生成加速器。 地址产生加速器响应于从指令排序单元接收的发起信号,计算并输出操作的操作数的第一和第二有效地址。

    Hardware wake-and-go mechanism for a data processing system
    78.
    发明授权
    Hardware wake-and-go mechanism for a data processing system 有权
    数据处理系统的硬件唤醒机制

    公开(公告)号:US08250396B2

    公开(公告)日:2012-08-21

    申请号:US12024595

    申请日:2008-02-01

    IPC分类号: G06F1/00 G06F1/32

    摘要: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

    摘要翻译: 为数据处理系统提供硬件唤醒机制。 唤醒机制识别一个编程成语,表示线程正在等待事件。 唤醒机制使用与事件相关联的目标地址来更新唤醒数组。 线程然后进入休眠状态直到事件发生。 唤醒阵列可以是内容可寻址存储器(CAM)。 当对称多处理(SMP)结构出现在CAM中的目标地址上修改值时,CAM返回存储目标地址的存储地址列表。 唤醒机制将这些存储地址与等待目标地址的线程相关联,并且可以唤醒等待事件的一个或多个线程。

    Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks
    79.
    发明授权
    Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks 有权
    执行设置操作以在处理器执行消息传递接口任务时接收不同数量的数据

    公开(公告)号:US08234652B2

    公开(公告)日:2012-07-31

    申请号:US11846154

    申请日:2007-08-28

    IPC分类号: G06F9/46 G06F15/173

    CPC分类号: G06F9/522 G06F9/5083

    摘要: Mechanisms are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so us to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.

    摘要翻译: 提供了用于在处理器执行消息传递接口(MPI)任务时执行用于接收不同数据量的设置操作的机制。 提供了用于调整处理器的处理工作负载的平衡的机制,使得我们最小化等待所有处理器调用同步操作的等待周期。 MPI负载平衡控制器维护一个历史记录,提供关于其对同步操作的调用的任务简档。 根据该信息,可以确定哪些处理器应该减轻其处理负载,哪些处理器能够处理额外的处理负载,而不会对并行执行系统的整体操作产生显着的负面影响。 结果,可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

    Method and apparatus for handling multiple memory requests within a multiprocessor system
    80.
    发明授权
    Method and apparatus for handling multiple memory requests within a multiprocessor system 有权
    用于在多处理器系统内处理多个存储器请求的方法和装置

    公开(公告)号:US08214603B2

    公开(公告)日:2012-07-03

    申请号:US12024181

    申请日:2008-02-01

    IPC分类号: G06F12/00 G06F13/00

    CPC分类号: G06F9/526

    摘要: A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.

    摘要翻译: 公开了一种在多处理器系统内处理多个存储器请求的方法。 锁控制部分最初被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求,确定数据块的锁定控制部分是否已经被设置。 如果已经设置了锁定控制部分,则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。 如果请求处理单元位于距存储器控制器超过预定距离的位置,则请求处理单元被邀请执行其他功能; 否则,请求处理单元的号码被放置在队列表中。 然而,如果锁定控制部分尚未设置,则数据块的锁定控制部分被设置,并且允许访问请求。