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    DMA (direct memory access) coalescing
    74.
    发明授权
    DMA (direct memory access) coalescing 有权
    DMA（直接内存访问）合并

    公开(公告)号：US08661167B2

    公开(公告)日：2014-02-25

    申请号：US12655311

    申请日：2009-12-29

    申请人： Chih-Fan Hsin ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai

    发明人： Chih-Fan Hsin ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai

    IPC分类号： G06F3/00 ,  G06F13/00

    CPC分类号： G06F1/3278 ,  G06F1/3209 ,  H04L12/12 ,  H04L49/90 ,  H04L49/9063 ,  Y02D10/157 ,  Y02D50/20 ,  Y02D50/40 ,  Y02D50/42

    摘要： In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.

    摘要翻译： 通常，在一个方面，一种方法包括至少部分地基于主机平台的功率睡眠状态来确定重复的周期性DMA（直接存储器访问）合并间隔。 该方法还包括在间隔期间在FIFO（先进先出）队列中接收的数据缓冲，并且在FIFO中排队的数据在重复的周期性期满之后将其写入设备外部的存储器 DMA合并间隔。

    NETWORK CONTROLLER CIRCUITRY TO DETERMINE, AT LEAST IN PART, WHETHER AT LEAST ONE POWER MANAGEMENT ACTION IS TO BE INITIATED
    76.
    发明申请
    NETWORK CONTROLLER CIRCUITRY TO DETERMINE, AT LEAST IN PART, WHETHER AT LEAST ONE POWER MANAGEMENT ACTION IS TO BE INITIATED 有权
    网络控制器电路至少部分确定，无论是至少一个电源管理操作都要启动

    公开(公告)号：US20120066520A1

    公开(公告)日：2012-03-15

    申请号：US12882956

    申请日：2010-09-15

    申请人： Chih-Fan Hsin ,  Shian Tsai, JR. ,  Tsung-Yuan C. Tai

    发明人： Chih-Fan Hsin ,  Shian Tsai, JR. ,  Tsung-Yuan C. Tai

    IPC分类号： G06F1/00

    CPC分类号： H04L12/12 ,  H04L41/0833 ,  Y02D50/40 ,  Y02D50/42

    摘要： An embodiment may include network controller circuitry that may be comprised, at least in part, in a host computer. The circuitry may determine, at least in part, based at least in part upon at least one comparison, whether at least one power management action is to be initiated. The at least one comparison may compare, at least in part, at least one pattern with at least one portion of at least one packet received, at least in part, by the host computer. The at least one power management action may include the modification, at least in part, of at least one power management configuration of the host computer. The modification may accommodate, at least in part, at least one packet processing latency policy associated, at least in part, with the at least one pattern. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    摘要翻译： 一个实施例可以包括网络控制器电路，其可以至少部分地包括在主计算机中。 该电路至少部分地至少部分地基于至少一个比较来确定是否启动至少一个电力管理动作。 至少一个比较可以至少部分地将至少一个模式与至少一个分组的至少一部分至少部分地由主计算机接收。 至少一个电源管理动作可以包括至少部分地修改主计算机的至少一个电源管理配置。 该修改可以至少部分地适应至少部分地与至少一个模式相关联的至少一个分组处理等待时间策略。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

    DMA (DIRECT MEMORY ACCESS) COALESCING
    77.
    发明申请
    DMA (DIRECT MEMORY ACCESS) COALESCING 有权
    DMA（直接存储器访问）COALESCING

    公开(公告)号：US20100153590A1

    公开(公告)日：2010-06-17

    申请号：US12655311

    申请日：2009-12-29

    申请人： Chih-Fan Hsin ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai

    发明人： Chih-Fan Hsin ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai

    IPC分类号： G06F13/28 ,  G06F13/24

    CPC分类号： G06F1/3278 ,  G06F1/3209 ,  H04L12/12 ,  H04L49/90 ,  H04L49/9063 ,  Y02D10/157 ,  Y02D50/20 ,  Y02D50/40 ,  Y02D50/42

    摘要： In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.

    摘要翻译： 通常，在一个方面，一种方法包括至少部分地基于主机平台的功率睡眠状态来确定重复的周期性DMA（直接存储器访问）合并间隔。 该方法还包括在间隔期间在FIFO（先进先出）队列中接收的数据缓冲，并且在FIFO中排队的数据在重复的周期性期满之后将其写入设备外部的存储器 DMA合并间隔。