公开(公告)号：US06798681B2

公开(公告)日：2004-09-28

申请号：US10256954

申请日：2002-09-27

Applicant: Richard Ferrant ,  Pascale Mazoyer ,  Pierre Fazan

Inventor： Richard Ferrant ,  Pascale Mazoyer ,  Pierre Fazan

IPC: G11C506

CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4097

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

Abstract translation: 由单元阵列形成的DRAM，每个单元包括电容存储点和控制晶体管。 该阵列由三行和三列延伸的基本图案的重复形成，并且包括六个单元，其布置成使得基本图案的三列和三列中的每一行都包括两个单元，其中单元的每列 图案包括第一位线和第二位线，每个第一和第二位线连接到由列包括的存储器单元的一半。

公开(公告)号：US06563749B2

公开(公告)日：2003-05-13

申请号：US09895026

申请日：2001-06-29

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C700

CPC classification number: G11C29/84

Abstract: A dynamic memory circuit including memory cells arranged in an array of rows and columns, each row capable of being activated by a word line and each column being formed of cells connected to a first and to a second bit lines, which includes at least one, spare row formed of static memory cells, adapted to being activated to replace a memory cell row, each spare cell being connected to the first and second bit lines of a column of the circuit.

公开(公告)号：US06538942B2

公开(公告)日：2003-03-25

申请号：US09883697

申请日：2001-06-18

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C700

CPC classification number: G11C11/4094

Abstract: Each memory cell of a memory device is connected to a bit line of a memory array and is associated with a read/rewrite amplifier connected between the bit line and a reference bit line. The bit line and the reference bit line are precharged to a predetermined precharge voltage. The content of a selected memory cell is read and refreshed based upon an associated read/rewrite amplifier. Between the precharging and the reading and refreshing, two capacitors previously charged to a charging voltage greater than the precharge voltage are respectively connected to the bit line and to the reference bit line.

公开(公告)号：US06316986B1

公开(公告)日：2001-11-13

申请号：US09578780

申请日：2000-05-25

Applicant: Richard Ferrant ,  Francois Jacquet

Inventor： Richard Ferrant ,  Francois Jacquet

IPC: G05F110

CPC classification number: H02M3/07

Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.

Abstract translation: 在充电阶段，通过与电容器（PC）的第一端子（T1）串联连接的两个互补充电晶体管（TR1，TR2）对电容器（PC）进行充电。 在电压倍增阶段，将输入电压（Vdd）输送到电容器的第二端子（T2），并且相对于输入电压增加的输出电压（Vout）在第一端子（T1）处被恢复 电容器和电容器在放电阶段被放电。 在三相期间，直接连接到电容器的第一端子（T1）的充电晶体管（TR2）的基板（BK2）被从属于同一充电晶体管（TR2）的源极（S2），同时仍然保持源极 基极结和该充电晶体管（TR2）的漏 - 基极结反向偏置。

公开(公告)号：US06208551B1

公开(公告)日：2001-03-27

申请号：US09425763

申请日：1999-10-22

Applicant: Hervé Jaouen ,  Richard Ferrant

Inventor： Hervé Jaouen ,  Richard Ferrant

IPC: G11C1124

CPC classification number: G11C11/401

Abstract: A DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, the insulator being coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.

Abstract translation: 以单体形式制造的DRAM，其单元包括MOS晶体管和电容器，其第二电极对同一行的所有电池是共同的并且被绝缘体覆盖，绝缘体涂覆有独立的导电元件分布 在相同的水平面上，两个相邻元件被偏置到相应的高和低电平。

公开(公告)号：US5898622A

公开(公告)日：1999-04-27

申请号：US970844

申请日：1997-11-14

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/062

Abstract: A memory read circuit includes an input to be connected to a bit line to which there are connected memory cells, and an output to produce an output logic potential. A current source produces a first current and a current-voltage converter produces the output logic potential. This potential represents the value of a second current obtained by the rerouting of a part of the first current towards the bit line when one of the cells is read, so that once the bit line is charged, the value of this second current is determined solely by the state of the selected cell and is independent of the equivalent capacitive load of the bit line.

Abstract translation: 存储器读取电路包括要连接到连接有存储单元的位线的输入端和产生输出逻辑电位的输出。 电流源产生第一电流，电流 - 电压转换器产生输出逻辑电位。 该电位表示当读取单元之一时通过将第一电流的一部分重新布置到位线而获得的第二电流的值，使得一旦位线被充电，该第二电流的值仅被确定 通过所选择的单元的状态并且独立于位线的等效容性负载。

公开(公告)号：US5862091A

公开(公告)日：1999-01-19

申请号：US898499

申请日：1997-07-22

Applicant: Thierry Bion ,  Richard Ferrant

Inventor： Thierry Bion ,  Richard Ferrant

IPC: G11C17/12 ,  G11C7/02

CPC classification number: G11C17/123

Abstract: A memory accessible in read mode only comprises storage elements designed to contain a bit that can assume two levels. Each memory cell comprises a transistor. The transistor of the storage element may include an associated circuit portion to prompt a short circuit between the drain and the source of the transistor if the storage element has to contain one bit at one of the two levels. Furthermore, the use of an unbalanced differential amplifier permits an improvement of the access time of the memory.

Abstract translation: 以读取模式访问的存储器仅包括设计成包含可以承担两个级别的位的存储元件。 每个存储单元包括晶体管。 存储元件的晶体管可以包括相关联的电路部分，以在存储元件必须在两个电平中的一个级别中包含一位时提示晶体管的漏极和源极之间的短路。 此外，使用不平衡差分放大器允许改善存储器的访问时间。

公开(公告)号：US5469485A

公开(公告)日：1995-11-21

申请号：US201034

申请日：1994-02-24

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: H03K21/38

CPC classification number: H03K21/38

Abstract: A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divide-by-two binary. A binary code C representing a decimal integer value V is applied to the divider circuit. The frequency divider comprises circuits that enable the performance of a variable order division (V+1, V, . . . V-p, where p is a whole number greater than or equal to 1 and smaller than N-1) for one and the same binary code C.

Abstract translation: 由N分频二进制构成的分频器包括逻辑电路，其能够通过第N次分频产生的最高有效位的状态变化来产生分频结束的信号， 二进制二进制。 代表十进制整数值V的二进制码C被施加到分频器电路。 分频器包括能够执行可变顺序划分（V + 1，V，...，Vp，其中p是大于或等于1并且小于N-1的整数）的电路， 二进制代码C.

公开(公告)号：US5410506A

公开(公告)日：1995-04-25

申请号：US274142

申请日：1994-07-14

Applicant: Richard Ferrant ,  Bruno Fel

Inventor： Richard Ferrant ,  Bruno Fel

IPC: G06F11/00 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC classification number: G11C11/419 ,  G06F11/00 ,  G11C7/12

Abstract: Disclosed is an integrated circuit memory comprising at least one column of memory cells parallel connected with one another and connected to at least one bit line, each memory cell being connected to a bit line by at least one access transistor, wherein said memory contains a protection transistor that is connected to the bit line and controlled so as to be made conductive so as to limit the voltage drop on the bit line, during the stages of the reading of the memory, when this drop in voltage goes beyond a threshold having a value smaller than a value that prompts the writing of an information element in a memory cell.

Abstract translation: 公开了一种集成电路存储器，包括彼此并联并连接到至少一个位线的至少一列存储器单元，每个存储单元由至少一个存取晶体管连接到位线，其中所述存储器包含保护 晶体管，其连接到位线并被控制为导通，以便在读取存储器的阶段期间限制位线上的电压降，当该电压下降超过具有值的阈值时 小于提示将信息元素写入存储单元的值。

公开(公告)号：US4707810A

公开(公告)日：1987-11-17

申请号：US818031

申请日：1986-01-13

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/789 ,  G11C29/83

Abstract: An integrated circuit memory is provided in which a repair circuit allows a redundant cell line to be substituted for a cell line which has proved defective. In the invention, access is had to the repair circuit by using the properties of the decoder of the memory. An instruction for decomposing a fuse is given, for all the repair circuits of the memory, through a single external terminal conected to a connection which serves all the repair circuits. When the fuse is decomposed, a bistable circuit changes state and switches the cell lines.

Abstract translation: 提供一种集成电路存储器，其中修复电路允许将冗余的单元线替代已证明有缺陷的细胞系。 在本发明中，通过使用存储器的解码器的属性来访问修复电路。 对于存储器的所有修复电路，通过连接到服务于所有修复电路的连接的单个外部端子，给出了用于分解熔丝的指令。 当保险丝分解时，双稳态电路改变状态并切换细胞系。