公开(公告)号：US06798681B2

公开(公告)日：2004-09-28

申请号：US10256954

申请日：2002-09-27

申请人： Richard Ferrant ,  Pascale Mazoyer ,  Pierre Fazan

发明人： Richard Ferrant ,  Pascale Mazoyer ,  Pierre Fazan

IPC分类号： G11C506

CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4097

摘要： A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

摘要翻译： 由单元阵列形成的DRAM，每个单元包括电容存储点和控制晶体管。 该阵列由三行和三列延伸的基本图案的重复形成，并且包括六个单元，其布置成使得基本图案的三列和三列中的每一行都包括两个单元，其中单元的每列 图案包括第一位线和第二位线，每个第一和第二位线连接到由列包括的存储器单元的一半。

公开(公告)号：US08299514B2

公开(公告)日：2012-10-30

申请号：US13285182

申请日：2011-10-31

申请人： Brent Keeth ,  Pierre Fazan

发明人： Brent Keeth ,  Pierre Fazan

IPC分类号： H01L29/94

CPC分类号： H01L27/10888 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10811

摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.

摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取。 存储器阵列中的至少一个包含至少100平方微米的具有至少128个功能和可操作寻址的存储器单元的连续管芯表面区域。 更优选地，至少100平方微米的连续管芯表面区域具有至少170个功能和可操作寻址的存储器单元。

公开(公告)号：US07736959B2

公开(公告)日：2010-06-15

申请号：US12069704

申请日：2008-02-12

申请人： Pierre Fazan

发明人： Pierre Fazan

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/845 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10897 ,  H01L27/1211 ,  H01L29/7841 ,  H01L29/785

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors). In another aspect, the present invention is directed to a method of manufacture of such integrated circuit device.

摘要翻译： 这里描述和说明了许多发明。 在第一方面，本发明涉及包括SOI逻辑晶体管和SOI存储晶体管的集成电路器件及其制造方法。 在一个实施例中，集成电路器件包括具有例如PD或FD SOI存储器单元的存储器部分和具有例如诸如Fin-FET，多个栅极晶体管和/或非高电压的高性能晶体管的逻辑部分 性能晶体管（例如不具有高性能晶体管的性能特性的单栅极晶体管）。 另一方面，本发明涉及这种集成电路装置的制造方法。

公开(公告)号：US20080237714A1

公开(公告)日：2008-10-02

申请号：US12053398

申请日：2008-03-21

申请人： Pierre Fazan

发明人： Pierre Fazan

IPC分类号： H01L27/12 ,  H01L21/84 ,  C23F1/00

CPC分类号： H01L27/10805 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10847 ,  H01L27/1203 ,  H01L29/7841

摘要： Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.

摘要翻译： 用于制造独立存储器件的制造工艺流程的实施例，其可以实现4F2或5F2的数量级的位单元尺寸，并且可以应用于公共源极/漏极，单独的源极/漏极或仅公共源极或仅公共漏极晶体管 阵列 有源区域和字线图案在绝缘体上硅衬底上形成为垂直布置的直线。 活动区域和字线间的交点定义用于连接通孔和金属线层的接触区域。 使用绝缘间隔物来提供蚀刻掩模图案，其允许将接触区域选择性地蚀刻为一系列线性沟槽，从而便于直线光刻技术。 制造过程的实施例在连续的处理步骤中去除第一层金属（金属-1）岛并形成细长的通孔以构建密集的存储器阵列。

公开(公告)号：US20080153213A1

公开(公告)日：2008-06-26

申请号：US12069704

申请日：2008-02-12

申请人： Pierre Fazan

发明人： Pierre Fazan

IPC分类号： H01L21/782

CPC分类号： H01L27/10894 ,  H01L21/845 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10897 ,  H01L27/1211 ,  H01L29/7841 ,  H01L29/785

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors). In another aspect, the present invention is directed to a method of manufacture of such integrated circuit device.

摘要翻译： 这里描述和说明了许多发明。 在第一方面，本发明涉及包括SOI逻辑晶体管和SOI存储晶体管的集成电路器件及其制造方法。 在一个实施例中，集成电路器件包括具有例如PD或FD SOI存储器单元的存储器部分，以及具有例如诸如Fin-FET，多个栅极晶体管和/或非高电位的高性能晶体管的逻辑部分 性能晶体管（例如不具有高性能晶体管的性能特性的单栅极晶体管）。 另一方面，本发明涉及这种集成电路装置的制造方法。

公开(公告)号：US07177175B2

公开(公告)日：2007-02-13

申请号：US11334338

申请日：2006-01-17

申请人： Pierre Fazan ,  Serguei Okhonin

发明人： Pierre Fazan ,  Serguei Okhonin

IPC分类号： G11C11/24 ,  H01L27/01

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

公开(公告)号：US06936549B2

公开(公告)日：2005-08-30

申请号：US10737500

申请日：2003-12-16

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L27/10852

摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

摘要翻译： 在半导体工艺中在半导体衬底上沉积多组分层。 多组分层可以是由气态钛有机金属前体，反应性硅烷基气体和气态氧化剂形成的电介质层。 多组分层可以沉积在冷壁或热壁化学气相沉积（CVD）反应器中，并且在存在或不存在等离子体的情况下。 多组分层也可以使用诸如辐射能或快速热CVD的其它过程进行沉积。

公开(公告)号：US06925006B2

公开(公告)日：2005-08-02

申请号：US10724377

申请日：2003-11-28

申请人： Pierre Fazan ,  Serguei Okhonin

发明人： Pierre Fazan ,  Serguei Okhonin

IPC分类号： G01T1/24 ,  G11C11/403 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786 ,  H01L31/10 ,  G11C16/04

CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

公开(公告)号：US5949117A

公开(公告)日：1999-09-07

申请号：US580459

申请日：1995-12-26

申请人： Gurtej Singh Sandhu ,  Pierre Fazan

发明人： Gurtej Singh Sandhu ,  Pierre Fazan

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7885 ,  H01L29/42324

摘要： In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region. The surface of the semiconductor substrate can be curved in the vicinity of the drain of the asymmetric transistor in order to permit the momentum of the charge carriers to facilitate penetration of the charge carriers into the gate.

公开(公告)号：US5491356A

公开(公告)日：1996-02-13

申请号：US153124

申请日：1993-11-15

申请人： Charles Dennison ,  Pierre Fazan

发明人： Charles Dennison ,  Pierre Fazan

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10817

摘要： A three dimensional capacitor structure particularly adapted for use as a memory cell capacitor of a DRAM is disclosed. The capacitor structure incorporates the substantially vertical (in relation to the substrate) sides of a plurality of spacers into the storage node capacitor to increase the total area of the storage node capacitor. In the described embodiments of the invention, a first spacer and a second spacer are formed next to the digit lines. The bottom storage node plate is formed on at least the first sides of the spacers to increase area of the storage node. The bottom storage node plate is also formed on the upper surface of the digit line. Additional spacers can also be added to further increase the area of the storage node. A dielectric layer is formed over the first capacitor plate and a second capacitor plate layer is formed over the dielectric layer to complete the structure.

摘要翻译： 公开了一种特别适用于DRAM的存储单元电容器的三维电容器结构。 电容器结构将多个间隔物的基本垂直（相对于衬底）侧面结合到存储节点电容器中，以增加存储节点电容器的总面积。 在本发明的所述实施例中，第一间隔件和第二间隔件形成在数字线的旁边。 底部存储节点板形成在间隔物的至少第一侧上以增加存储节点的面积。 底部存储节点板也形成在数字线的上表面上。 还可以添加附加的间隔物以进一步增加存储节点的面积。 在第一电容器板上形成电介质层，在电介质层上方形成第二电容器板层以完成该结构。