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公开(公告)号：US06792488B2
公开(公告)日：2004-09-14
申请号：US10440079
申请日：2003-05-15
IPC分类号： G06F1300
CPC分类号： G06F13/4269
摘要： A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus.
摘要翻译： 在第一和第二处理器之间进行通信的方法包括：第一处理器通过公共控制总线发送数据，第二处理器从公共控制总线接收数据。
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72.发明授权Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture 失效采用智能逻辑模型来实现简洁的逻辑表示，以便设计描述清晰，并能快速设计公开(公告)号：US06721925B2
公开(公告)日：2004-04-13
申请号：US10025193
申请日：2001-12-18
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
摘要翻译： 代表逻辑设备通常包括创建逻辑设备的模型，其中模型表示逻辑设备的变体的集合。 可以在逻辑设计中使用该模型的表示，并且可以基于对表示形成的连接来自动选择逻辑设备的特定变体。 可以自动检测连接错误，并且当检测到连接错误时可以自动显示第一指示。 当修正连接错误时，可以自动显示与第一指示不同的第二指示。
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公开(公告)号：US06687246B1
公开(公告)日：2004-02-03
申请号：US09387047
申请日：1999-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , John Cyr
发明人： Gilbert Wolrich , Matthew J. Adiletta , John Cyr
IPC分类号： H04Q1100
CPC分类号： H04L49/10 , H04L49/101 , H04L49/254 , H04L49/3045 , H04L49/45
摘要： A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.
摘要翻译： 交换结构包括每个具有多个输入端口和多个输出端口的第一多个数据开关，所述多个开关能够将其任何输入端口切换到其任何输出端口，并且所述多个数据开关具有耦合的输入 到多个输入总线，使得输入总线中的第一个的第一字节耦合到多个开关中的第一个，并且第一输入总线的后续字节耦合到多个输入总线中的后一个 开关。
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公开(公告)号：US06631430B1
公开(公告)日：2003-10-07
申请号：US09473113
申请日：1999-12-28
IPC分类号： G06F1200
CPC分类号： G06F13/385 , Y10S370/912
摘要： Receiving bytes of data from a media device includes issuing N consecutive requests, each for M-bytes, to the media device and receiving N−1 responses of M bytes of data from the media device.
摘要翻译： 从媒体设备接收数据字节包括向媒体设备发送N个连续请求，每个M个字节用于M字节，并从媒体设备接收M字节数据的N-1个响应。
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公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用 被读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
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公开(公告)号：US06587906B2
公开(公告)日：2003-07-01
申请号：US10339221
申请日：2003-01-09
IPC分类号： G06F1300
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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77.发明授权公开(公告)号：US06532509B1
公开(公告)日：2003-03-11
申请号：US09470541
申请日：1999-12-22
IPC分类号： G06F1314
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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78.发明授权SRAM controller for parallel processor architecture including address and command queue and arbiter 有权用于并行处理器架构的SRAM控制器，包括地址和命令队列和仲裁器公开(公告)号：US06427196B1
公开(公告)日：2002-07-30
申请号：US09387110
申请日：1999-08-31
IPC分类号： G06F1300
CPC分类号： G06F13/1642
摘要： A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
摘要翻译： 用于随机存取存储器的控制器包括保存来自多个微控制功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。
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公开(公告)号：US06324624B1
公开(公告)日：2001-11-27
申请号：US09473798
申请日：1999-12-28
IPC分类号： G06F1318
CPC分类号： G06F9/52
摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the read lock miss queue contains at least one read lock memory reference request.
摘要翻译： 管理对随机存取存储器的存储器访问包括获取读锁定存储器引用请求并将读锁定存储器引用请求放置在读锁定未命中队列的末尾，如果（1）读锁定存储器引用请求正在请求访问解锁的存储器位置 和（2）读取锁定未命中队列至少包含一个读取锁定存储器引用请求。
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公开(公告)号：US20200073846A1
公开(公告)日：2020-03-05
申请号：US16366496
申请日：2019-03-27
申请人： Matthew J. Adiletta , Bradley Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mizra , Jose Niell , Thomas E. Willis , William Duggan
发明人： Matthew J. Adiletta , Bradley Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mizra , Jose Niell , Thomas E. Willis , William Duggan
摘要： Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.
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