公开(公告)号：US5600847A

公开(公告)日：1997-02-04

申请号：US475162

申请日：1995-06-07

申请人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

发明人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

IPC分类号： G06F7/57 ,  G06F7/38

CPC分类号： G06F7/57

摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 可控制的换档器是桶旋转器（235）的替代品。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

公开(公告)号：US5592405A

公开(公告)日：1997-01-07

申请号：US484579

申请日：1995-06-07

申请人： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

发明人： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

IPC分类号： G06F15/167 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F7/38 ,  G06F7/00 ,  G06F7/50

CPC分类号： G06F15/17375 ,  G06F12/0284

摘要： A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.

摘要翻译： 一种数据处理装置，包括被分成多个部分的算术逻辑单元。 每个部分在相应的输出处产生表示第一和第二多位数字输入的各个子集的组合的数字结果信号。 算术逻辑单元包括状态检测器，其产生指示算术逻辑单元的相应部分的所述数字结果信号的单位状态信号。 这些单位状态信号存储在多标志寄存器内的预定位置。 选项寄存器存储从算术逻辑单元划分到的多个可能数量的区段中选择的区段数量的指示。 算术逻辑单元还连接到多标志寄存器，使得每个部分选择输出第一多位数字输入或第二多位数字输入的对应位，取决于多标志寄存器中对应的单个状态位的数字状态 。 这种技术允许各种功能，如饱和度，最大值，像素透明度和颜色扩展等。

公开(公告)号：US5592231A

公开(公告)日：1997-01-07

申请号：US477743

申请日：1995-06-07

申请人： Todd Clatanoff ,  Vishal Markandey ,  Robert J. Gove ,  Kazuhiro Ohara

发明人： Todd Clatanoff ,  Vishal Markandey ,  Robert J. Gove ,  Kazuhiro Ohara

IPC分类号： H04N7/01 ,  G06T7/20 ,  H04N5/44

CPC分类号： H04N7/012

摘要： A method for processing video data to produce a progressively scanned signal from an input of conventional interlaced video. The data is received at a processor (1), used to determine a motion signal (26) over time between field of the data. The motion signal is filtered to reduce errors caused by noise-corrupted video sources and then further filtered to spread out the determined motion signal. Edge information (30) is located and combined with the motion signal to produce an integrated progressive-scan signal (36) for display on a video display device, producing images with sharper edges and motion signals which have a lower susceptibility to noise.

公开(公告)号：US5592188A

公开(公告)日：1997-01-07

申请号：US368448

申请日：1995-01-04

申请人： Donald B. Doherty ,  Robert J. Gove

发明人： Donald B. Doherty ,  Robert J. Gove

IPC分类号： G02B7/00 ,  G02B26/08 ,  G09G3/34 ,  H04N9/31 ,  H04N9/12 ,  G02F1/00

CPC分类号： G09G3/346 ,  G02B26/008 ,  G02B26/0841 ,  H04N9/3114 ,  G09G2310/0235 ,  G09G2320/0276

摘要： A method and system for accentuating intense white display areas in sequential DMD video systems includes generating a special signal for each pixel that indicates whether to boost the intensity of that pixel in all colors. The method further includes enabling the mirrors to be turned on during times of color boundary of the color wheel such that DMD with mirrors receives different mixes of color light that are integrated together to produce intense white. The system may include degamma lookup tables for each color. The degamma lookup tables are augmented when the special signal is generated.

摘要翻译： 用于在连续DMD视频系统中强调强烈的白色显示区域的方法和系统包括为指示是否提高所有颜色的该像素的强度的每个像素生成特殊信号。 该方法还包括使得在色轮的颜色边界的时间期间可以打开反射镜，使得具有反射镜的DMD接收不同颜色的混合物，这些混合物被集成在一起以产生强烈的白色。 该系统可以包括针对每种颜色的色度查找表。 当产生特殊信号时，增强查询表。

公开(公告)号：US5590350A

公开(公告)日：1996-12-31

申请号：US159282

申请日：1993-11-30

申请人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

发明人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

IPC分类号： G06F7/57 ,  G06F9/00 ,  H03K19/00

CPC分类号： G06F7/57

摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 可控制的换档器是桶旋转器（235）的替代品。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

公开(公告)号：US5519450A

公开(公告)日：1996-05-21

申请号：US339098

申请日：1994-11-14

申请人： Paul M. Urbanus ,  Donald B. Doherty ,  Robert J. Gove ,  Gregory J. Hewlett ,  Stephen G. Kalthoff

发明人： Paul M. Urbanus ,  Donald B. Doherty ,  Robert J. Gove ,  Gregory J. Hewlett ,  Stephen G. Kalthoff

IPC分类号： H04N5/45 ,  G09G3/34 ,  G09G5/00 ,  G09G5/02 ,  G09G5/06 ,  G09G5/377 ,  H04N5/74 ,  H04N9/30 ,  H04N9/76

CPC分类号： H04N9/30 ,  G09G5/02 ,  H04N5/7458 ,  G09G2340/10 ,  G09G3/346

摘要： An SLM-based digital display system (10) having a graphics display subsystem (13 and 18) for closed captioning, on-screen displays, and other graphics images that are overlaid on the video image. The graphics display subsystem (13 and 18) has a graphics processor (21) that prepares the graphics data, which is inserted into the video data path after video data processing and prior to a look-up table unit (27). A select logic unit (24) provides a control signal to a multiplexer (26) that selects between video data and graphics data for input to the look-up table unit (27). The look-up table unit (27) performs its mapping according to the type of data received, such as by linearizing video data or palletizing graphics data.

摘要翻译： 一种基于SLM的数字显示系统（10），具有用于隐藏字幕的图形显示子系统（13和18），屏幕显示和覆盖在视频图像上的其他图形图像。 图形显示子系统（13和18）具有图形处理器（21），其准备图形数据，其在视频数据处理之后并在查找表单元（27）之前被插入到视频数据路径中。 选择逻辑单元（24）向多路复用器（26）提供控制信号，多路复用器选择视频数据和图形数据，以输入到查找表单元（27）。 查找表单元（27）根据所接收的数据的类型来执行其映射，例如通过线性化视频数据或码垛图形数据。

公开(公告)号：US5508750A

公开(公告)日：1996-04-16

申请号：US383349

申请日：1995-02-03

申请人： Gregory J. Hewlett ,  Robert J. Gove

发明人： Gregory J. Hewlett ,  Robert J. Gove

IPC分类号： G06T9/00 ,  G11B27/031 ,  H04N5/14 ,  H04N5/44 ,  H04N5/74 ,  H04N7/01 ,  H04N7/26

CPC分类号： H04N5/147 ,  G11B27/031 ,  H04N19/142 ,  H04N19/179 ,  H04N19/46 ,  H04N19/85 ,  H04N19/87 ,  H04N5/7458 ,  H04N7/0112 ,  H04N7/012

摘要： A method of encoding video display data, after that data has been previously converted from a film frame rate to a faster video frame rate, such as by 3:2 pulldown. The data is first re-converted to the film frame format, as progressive frames (21). This progressive frame data is processed to determine where scene cuts occur (22). The data is then encoded consistent with MPEG encoding techniques, but with the scene cut information being used to begin groups of pictures (GOPs) at scene cuts and to determine where intrapictures, predicted pictures, or interpolated pictures shall occur (23).

摘要翻译： 一种编码视频显示数据的方法，之后数据已经预先从电影帧速率转换为更快的视频帧率，例如通过3：2下拉。 数据首先被重新转换为电影帧格式，作为渐进帧（21）。 处理该渐进帧数据以确定场景切割发生的位置（22）。 然后将数据与MPEG编码技术一致地编码，但是场景切割信息用于在场景切割时开始图像组（GOP），并确定图像内部，预测图像或内插图像应发生的位置（23）。

公开(公告)号：US5489952A

公开(公告)日：1996-02-06

申请号：US91852

申请日：1993-07-14

申请人： Robert J. Gove ,  Jeffrey B. Sampsell ,  Vishal Markandey

发明人： Robert J. Gove ,  Jeffrey B. Sampsell ,  Vishal Markandey

IPC分类号： H04N5/46 ,  H04N5/44 ,  H04N5/74 ,  H04N7/01

CPC分类号： H04N7/0122 ,  H04N5/7458

摘要： A multi-format display system including hardware and algorithms for digital and High Definition Television. The system includes a light source (120), a tuner/preprocessor unit (114), a processor unit (116), a spatial light modulator (118), and a display surface (128). The processor unit can scale and format the data for a number of standardized-format video broadcast signals, and can perform additional interpolation to eliminate artifacts.

公开(公告)号：US5487146A

公开(公告)日：1996-01-23

申请号：US209124

申请日：1994-03-08

申请人： Karl M. Guttag ,  Sydney W. Poland ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read

发明人： Karl M. Guttag ,  Sydney W. Poland ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read

IPC分类号： G06F13/28 ,  G09G5/393 ,  G06F12/06

CPC分类号： G06F13/28 ,  G09G5/393

摘要： A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may add the address value to the prior block starting address or add the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses.

摘要翻译： 数据处理装置包括存储器，控制电路，引导表和地址产生电路。 控制电路接收分组传送请求和分组传送参数。 分组传送参数包括起始地址，定义地址块的维度值，具有指导表条目的指南表和表指针。 每个指南表项具有地址值。 表指针最初指向指南表中的第一个指南表项。 地址生成电路形成与每个指导表条目对应的用于存储器访问的地址块的集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。 地址块由维度值形成。 在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。 地址产生电路可以将地址值添加到先前块开始地址，或者将引导表值添加到起始地址。 存储器访问可以是从地址块读取的存储器或写入地址块的存储器。

公开(公告)号：US5442411A

公开(公告)日：1995-08-15

申请号：US176618

申请日：1994-01-03

申请人： Paul M. Urbanus ,  Vishal Markandey ,  Robert J. Gove

发明人： Paul M. Urbanus ,  Vishal Markandey ,  Robert J. Gove

IPC分类号： H04N5/74

CPC分类号： H04N5/7458

摘要： An SLM-based video receiver (10) receives a video input on a field-by-field basis at a signal interface unit (11) and passes the input to a processor (12). The processor (12) performs analog-to-digital conversion if the pixel data is analog and also performs other enhancements to prepare the pixel data for loading into a video memory (14). Pixel data from the processor (12), representing a field of pixel data, is stored into the memory (14) for loading into rows of pixel elements of a spatial light modulator (16). The spatial light modulator (16) receives the pixel data in rows. The addressing functions of the spatial light modulator (16) are used to generate additional display rows of pixel data per field. Thus, the SLM-based video receiver (10) displays a video frame having more lines than the field of pixel data.

摘要翻译： 基于SLM的视频接收器（10）在信号接口单元（11）逐场接收视频输入，并将输入传递给处理器（12）。 如果像素数据是模拟的，则处理器（12）执行模数转换，并且还执行其他增强以准备用于加载到视频存储器（14）中的像素数据。 表示像素数据的场的来自处理器（12）的像素数据被存储到存储器（14）中，用于加载到空间光调制器（16）的像素元件行中。 空间光调制器（16）以行的形式接收像素数据。 空间光调制器（16）的寻址功能用于每场产生像素数据的附加显示行。 因此，基于SLM的视频接收器（10）显示具有比像素数据的场多的行的视频帧。