公开(公告)号：US5734880A

公开(公告)日：1998-03-31

申请号：US480230

申请日：1995-06-07

Applicant: Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

Inventor： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

IPC: G06F5/01 ,  G06F9/302 ,  G06F9/305 ,  G06F9/308 ,  G06F9/315 ,  G06F9/32 ,  G06F12/02 ,  G06F15/00

CPC classification number: G06F9/30014 ,  G06F12/0284 ,  G06F5/015 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30167 ,  G06F9/325

Abstract: Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop. count register. If this is zero then the loop priority logic reloads the program counter (701) with the loop start address and repeats the loop. If this is nonzero, program counter (701) may increment normally or will be loaded with the loop start address of a higher priority loop.

Abstract translation: 条件硬件分支采用零开销循环逻辑并写入程序循环内的循环计数寄存器。 零开销循环逻辑包括程序计数器（701），循环结束寄存器（711,712,713），循环开始寄存器（721,722,723），循环计数器寄存器（731,732,733），比较器（715， 716,717）和循环优先级逻辑（725）。 通常，每个周期递增程序计数器（701）。 比较器（715,716,717）将存储在程序计数器（701）中的地址与相应的循环结束寄存器（711,712,713）进行比较。 如果程序计数器（701）中的地址等于循环结束地址，则循环优先级逻辑（725）递减循环计数寄存器，并加载循环起始寄存器中循环起始地址的程序计数器。 硬件循环涉及在程序循环操作期间加载循环计数寄存器。 算术逻辑单元操作产生加载到状态寄存器中的状态位或分割成部分，并且生成用于加载循环的多标志寄存器（211）中存储的每个部分的状态位。 计数寄存器 如果这是零，则循环优先级逻辑使用循环起始地址重新加载程序计数器（701）并重复循环。 如果这是非零的，则程序计数器（701）可以正常地增加或将加载较高优先级循环的循环起始地址。

公开(公告)号：US5560030A

公开(公告)日：1996-09-24

申请号：US208413

申请日：1994-03-08

Applicant: Karl M. Guttag ,  Christopher J. Read ,  Sydney W. Poland ,  Robert J. Gove ,  Jeremiah E. Golston

Inventor： Karl M. Guttag ,  Christopher J. Read ,  Sydney W. Poland ,  Robert J. Gove ,  Jeremiah E. Golston

IPC: G06F13/28 ,  G09G5/393 ,  G06F13/00

CPC classification number: G06F13/28 ,  G09G5/393

Abstract: Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be transferred. A comparator compares recalled data to stored transparency data and indicates whether data to be transferred is to be written to memory. Destination address controller writes data to be transferred into memory at calculated destination addresses if the comparator indicates data to be transferred is to be written to memory. The recalled data is stored in a source register for comparison. In the preferred embodiment data is not written into memory if it matches the transparency data. The transparency register may store a multiple of the minimum amount of data to be transferred. The data to be transferred is organized into data words having a selected size. This selected size is an integral multiple of a minimum amount of data to be transferred. The comparator includes plural data comparators, where each data comparator compares the minimum amount of data to be transferred with a corresponding part of the transparency data. A multiplexer receives these comparison signals and an indication of the selected data size. The multiplexer provides indications of whether the data to be transferred is to be written to memory equal to the number of times the data words of the selected size fit within the transparency register. The selected data size may be a byte, a halfword, a word (32 bits) and a double word and the transparency register stores 64 bits.

Abstract translation: 数据处理器带有透明度检测数据传输控制器。 透明度寄存器存储透明度数据。 源地址控制器计算要转移的数据的调用的源地址。 比较器将回收的数据与存储的透明度数据进行比较，并指示要传送的数据是否要写入存储器。 如果比较器指示要传送的数据要写入存储器，则目的地址控制器将要传送到计算出的目标地址的数据写入存储器。 被调用的数据存储在源寄存器中进行比较。 在优选实施例中，如果它与透明度数据相匹配，则数据不被写入存储器。 透明度寄存器可以存储要传送的最小数据量的倍数。 要传送的数据被组织成具有选定尺寸的数据字。 该选择的大小是要传送的最小数据量的整数倍。 比较器包括多个数据比较器，其中每个数据比较器将要传输的最小数据量与透明度数据的相应部分进行比较。 多路复用器接收这些比较信号和所选数据大小的指示。 复用器提供指示要被传送的数据是否被写入存储器，等于所选择尺寸的数据字在透明度寄存器内的数目。 选择的数据大小可以是字节，半字，字（32位）和双字，透明度寄存器存储64位。

公开(公告)号：US5442581A

公开(公告)日：1995-08-15

申请号：US324323

申请日：1994-10-17

Applicant: Sydney W. Poland

Inventor： Sydney W. Poland

IPC: G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F2207/382 ,  G06F2207/5353

Abstract: An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2.sup.M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2.sup.M -1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.

Abstract translation: 每次迭代形成多个商位的迭代分割技术。 数据处理装置（1100）包括存储除数的第一寄存器（1101），初始存储分子（1103）的第二寄存器，多个全加法器（1112,1113,1114,1115,1116,1117,1118）和 相等数量的负检测器（1122,1123,1124,1125,1126,1127,1128）和循环计数器（1131）。 最初，全加器（1112,1113,1114,1115,1116,1117,1118）计算除数的每个积分积，而不是1和2M-1之间的2的幂，其中M是要计算的商比特数 。 这些因素存储在锁存器（1144,1146,1144,7118）中。 完全加法器（1112,1113,1114,1115,1116,1117,1118）并行地从1和2M-1之间的除数的每个积分乘积与分子的最高有效位并行地减去。 连接到每个全加器（1112,1113,1114,1115,1116,1117,1118）的负检测器（1122,1123,1124,1125,1126,1127,1128）表示第一非负差，其确定多个位 商和部分余数。 重复该过程，其中部分剩余左移M位置用作分子，基于所使用的数字的大小和每次迭代的位数。 对于有符号除法，商的符号被设置为分子和除数的检测的（1102,1104）相应符号的异或。

公开(公告)号：US4153937A

公开(公告)日：1979-05-08

申请号：US783903

申请日：1977-04-01

Applicant: Sydney W. Poland

Inventor： Sydney W. Poland

IPC: G06F15/02 ,  G06F9/00 ,  G06F9/26 ,  G06F3/08

CPC classification number: G06F9/262 ,  G06F9/26

Abstract: A microprocessor system with high order capabilities is provided with the two non-volatile memories which are read-only-memories (ROMs) in the disclosed embodiment. A first ROM stores the microcode for controlling the operation of the microprocessor circuits. The second ROM, which is preferably disposed in a module or cartridge, stores a plurality of program codes which are used to address the first ROM. The second ROM's module may be inserted into a receptacle for interconnecting it with the remainder of the microprocessor system. Preferably, a plurality of such second ROMs are available for selectively plugging into the microprocessor system.Further, a particular embodiment of the microprocessor system with high order capabilities for use as an electronic calculator with high order capabilities is disclosed in great detail.

Abstract translation: 在所公开的实施例中，具有高阶功能的微处理器系统被提供有作为只读存储器（ROM）的两个非易失性存储器。 第一ROM存储用于控制微处理器电路的操作的微代码。 优选地设置在模块或盒中的第二ROM存储用于寻址第一ROM的多个程序代码。 第二个ROM的模块可以插入插座中，以将其与微处理器系统的其余部分相互连接。 优选地，多个这样的第二ROM可用于选择性地插入微处理器系统。

公开(公告)号：US5974539A

公开(公告)日：1999-10-26

申请号：US160298

申请日：1993-11-30

Applicant: Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Phillip Moyse

Inventor： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Phillip Moyse

IPC: G06F5/01 ,  G06F9/302 ,  G06F9/315

CPC classification number: G06F9/30167 ,  G06F5/015

Abstract: A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.

Abstract translation: 三输入算术逻辑单元（230）产生由功能信号选择的三个输入的组合。 第二输入信号来自可控移位器（235）。 移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。 一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是移位量。 移位（235）的输出可以独立于算术逻辑单元（230）结果存储。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

公开(公告)号：US5696959A

公开(公告)日：1997-12-09

申请号：US478129

申请日：1995-06-07

Applicant: Karl M. Guttag ,  Sydney W. Poland ,  Keith Balmer

Inventor： Karl M. Guttag ,  Sydney W. Poland ,  Keith Balmer

IPC: G06T1/60 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30101 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30094 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3842

Abstract: A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0". In a further embodiment the register pair conditional write instruction is conditional. The write operation aborts if the designated condition is true. In the preferred embodiment of this invention, the arithmetic logic unit (230), the status register (210), the data registers (200) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71) as a part of a multiprocessor formed in a single integrated circuit (100) used in image processing.

Abstract translation: 存储器存储操作来自由算术逻辑单元条件选择的一对寄存器之一。 如果选择的状态位具有第一状态并且将与第一寄存器相关联的第二寄存器中的数据存储到存储器中，则指令逻辑电路（250,660）控制寻址电路（120）将第一寄存器中的数据存储到存储器中，如果 所选状态位响应于寄存器对条件存储指令具有第二状态。 这些位可以指示算术逻辑单元（230）的负输出，进位信号，溢出或零输出。 寄存器对条件存储指令指定用于控制条件存储的特定一个状态位。 指令逻辑电路（250,660）将选择的状态位替换为寄存器编号的最低有效位。 因此，如果状态位为“1”，则存储器来自第一寄存器，如果状态位为“0”，则来自第二寄存器。 在另一实施例中，寄存器对条件写指令是有条件的。 如果指定的条件为真，则写入操作中止。 在本发明的优选实施例中，算术逻辑单元（230），状态寄存器（210），数据寄存器（200）和指令解码逻辑（250,660）被体现在至少一个数字图像/图形处理器 （71）作为在图像处理中使用的单个集成电路（100）中形成的多处理器的一部分。

公开(公告)号：US5644524A

公开(公告)日：1997-07-01

申请号：US160120

申请日：1993-11-30

Applicant: Jerry R. Van Aken ,  Karl M. Guttag ,  Sydney W. Poland

Inventor： Jerry R. Van Aken ,  Karl M. Guttag ,  Sydney W. Poland

IPC: G06F7/52 ,  G06F7/74

CPC classification number: G06F7/74 ,  G06F7/535 ,  G06F2207/5353 ,  G06F7/49936

Abstract: This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to "0". Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is "1". If the difference is less than zero, then the next quotient bit is "0". The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0". Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.

Abstract translation: 本发明是用于划分的迭代技术。 除数具有N位，分子具有大于N位，通常为2N位。 每个迭代包括对分子的N个最高有效位的最左一位（1011,1035）的位置的初始检测。 如果该L不为零，则左移中的分子移动了L个位置（1016,1033），下一个L乘数位被设置为零，并且除法的完成迭代次数增加了L.替代实施例检测位 分子和除数的N个最高有效位的最左边的一个的最左边的位置。 如果这是非零的，则分子移动这个位数，相应的商位被设置为“0”。 接下来，分割技术计算分子的N个最高有效位与除数之间的差。 如果差值大于或等于零，则下一个商位为“1”。 如果差值小于零，则下一个商位为“0”。 如果该差值大于或等于零，则该差值代替分子的N个最高有效位。 然后分子左移一个位置。 这些迭代重复，直到迭代次数超过N.然后商完全形成，最后一个分子的数据是除法的剩余部分。 这种技术消除了这种技术确定商位为“0”的情况下的无用数据操作。 使用前处理和后处理可以使用带有签名的数字。 在本发明的优选实施例中，分割逻辑体现在至少一个数字图像/图形处理器中，作为在图像处理中使用的单个集成电路中形成的多处理器的一部分。

公开(公告)号：US5640578A

公开(公告)日：1997-06-17

申请号：US158742

申请日：1993-11-30

Applicant: Keith Balmer ,  Nicholas Ing-Simmons ,  Karl M. Guttag ,  Robert J. Gove ,  Jeremiah E. Golston ,  Christopher J. Read ,  Sydney W. Poland

Inventor： Keith Balmer ,  Nicholas Ing-Simmons ,  Karl M. Guttag ,  Robert J. Gove ,  Jeremiah E. Golston ,  Christopher J. Read ,  Sydney W. Poland

IPC: G06F3/153 ,  G06F7/575 ,  G06F9/302 ,  G06F9/318 ,  G06F9/32 ,  G06F12/08 ,  G06T1/00 ,  G06T1/20 ,  G06T11/00 ,  G09G5/39 ,  H04N1/387 ,  G06F7/38 ,  G06F7/50

CPC classification number: G06F7/575 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30189 ,  G06F9/30192 ,  G06F2207/382 ,  G06F2207/3828 ,  G06F7/49905

Abstract: An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections. The status detector supplies carry outs from each elementary section (301, 302, 303, 304) not coupled to an adjacent elementary section (301, 302, 303, 304) to the flags register (211). Status signals stored in the flags register (211) influence the combination of inputs formed by the arithmetic logic unit (230) within corresponding sections. An expand circuit (238) expands selected bits of flags register (211) to form a third input to a three input arithmetic logic unit (230).

Abstract translation: 算术逻辑单元（230）可以被划分为多个独立部分（301,302,303,340）。 对应于存储在标志寄存器（211）中的每个部分的进位状态信号的位零，其优选地包括比算术逻辑单元（230）的最大部分数量多的位。 新的状态信号可以覆盖先前的状态信号或旋转存储的比特并存储新的状态信号。 状态寄存器（210）存储确定算术逻辑单元（230）的段数的大小指示符。 状态检测器对于算术逻辑单元（230）的每个基本部分（301,302,303,304）具有零检测器（321,322,323,324）。 当小于最大数量的部分时，这些零信号为“与”（331,332,341）。 多路复用器将基本（311,312,313,314）的进位输出耦合到相邻基本部分（301,302,303,304）的进位，或者不依赖于所选择的部分数量。 状态检测器从没有耦合到相邻基本部分（301,302,303,304）的每个基本部分（301,302,303,304）提供进位到标志寄存器（211）。 存储在标志寄存器（211）中的状态信号影响由相应部分内的算术逻辑单元（230）形成的输入的组合。 扩展电路（238）扩展标志寄存器（211）的所选位以形成三输入算术逻辑单元（230）的第三输入。

公开(公告)号：USRE30671E

公开(公告)日：1981-07-07

申请号：US55888

申请日：1979-07-09

Applicant: Sydney W. Poland

Inventor： Sydney W. Poland

IPC: G06F9/24 ,  G06F15/02

CPC classification number: G06F9/24 ,  G06F15/02

Abstract: A microprocessor system with high order capabilities is provided with the two non-volatile memories which are read-only-memories (ROMs) in the disclosed embodiment. A first ROM stores the microcode for controlling the operation of the microprocessor circuits. The second ROM, which is preferably disposed in a module or cartridge, stores a plurality of program codes which are used to address the first ROM. The second ROM's module may be inserted into a receptacle for interconnecting it with the remainder of the microprocessor system. Preferably, a plurality of such second ROMs are available for selectively plugging into the microprocessor system.Further, a particular embodiment of the microprocessor system with high order capabilities for use as an electronic calculator with high order capabilities is disclosed in great detail.

公开(公告)号：US4139893A

公开(公告)日：1979-02-13

申请号：US826789

申请日：1977-08-22

Applicant: Sydney W. Poland

Inventor： Sydney W. Poland

IPC: G06F15/02 ,  G06F21/00

CPC classification number: G06F21/79 ,  G06F15/02

Abstract: A calculator program is stored on a magnetic recording medium or in a memory such as a read-only-memory. The program is read into or coupled to a programmable calculator for controlling the programmable calculator. A calculator program security system is provided whereby a security code is stored along with the program. If the security code is set, then the program cannot be examined by an operator of the calculator but the program may still be used to control the calculator. If the security code is not set, the operator may examine the program by using the calculator's learn mode. By setting the security code when the program is first stored on the magnetic recording medium or in the aforementioned memory, a proprietary program may be protected from someone using the programmable calculator to obtain a copy of the proprietary program.

Abstract translation: 计算器程序存储在磁记录介质或诸如只读存储器的存储器中。 将程序读入或耦合到可编程计算器，用于控制可编程计算器。 提供了一种计算器程序安全系统，其中安全代码与程序一起存储。 如果设置了安全码，则程序不能被计算器的操作者检查，但程序仍可用于控制计算器。 如果安全码未设置，操作员可以使用计算器的学习模式来检查程序。 通过在程序首先存储在磁记录介质或上述存储器中时设置安全代码，可以使用可编程计算器来保护专有程序以获得专有程序的副本。